ARM: OMAP: implement CPUfreq frequency table based on PRCM table

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-omap / clock.h

diff --git a/include/asm-arm/arch-omap/clock.h b/include/asm-arm/arch-omap/clock.h
index f83003f5287b04dbd63b3998ea8e98beae0b7286..971d167b5eba7c4ac6a0750af056a051d4785a4c 100644 (file)
--- a/include/asm-arm/arch-omap/clock.h
+++ b/include/asm-arm/arch-omap/clock.h
@@ -10,10 +10,43 @@
  * published by the Free Software Foundation.
  */
 
+#include <linux/cpufreq.h>
+
 #ifndef __ARCH_ARM_OMAP_CLOCK_H
 #define __ARCH_ARM_OMAP_CLOCK_H
 
 struct module;
+struct clk;
+
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+
+struct clksel_rate {
+       u8                      div;
+       u32                     val;
+       u8                      flags;
+};
+
+struct clksel {
+       struct clk               *parent;
+       const struct clksel_rate *rates;
+};
+
+struct dpll_data {
+       void __iomem            *mult_div1_reg;
+       u32                     mult_mask;
+       u32                     div1_mask;
+       void __iomem            *div2_reg;
+       u32                     div2_mask;
+#  if defined(CONFIG_ARCH_OMAP3)
+       void __iomem            *control_reg;
+       u32                     enable_mask;
+       u8                      auto_recal_bit;
+       u8                      recal_en_bit;
+       u8                      recal_st_bit;
+#  endif
+};
+
+#endif
 
 struct clk {
        struct list_head        node;
@@ -25,8 +58,6 @@ struct clk {
        __u32                   flags;
        void __iomem            *enable_reg;
        __u8                    enable_bit;
-       __u8                    rate_offset;
-       __u8                    src_offset;
        __s8                    usecount;
        void                    (*recalc)(struct clk *);
        int                     (*set_rate)(struct clk *, unsigned long);
@@ -34,6 +65,16 @@ struct clk {
        void                    (*init)(struct clk *);
        int                     (*enable)(struct clk *);
        void                    (*disable)(struct clk *);
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+       u8                      fixed_div;
+       void __iomem            *clksel_reg;
+       u32                     clksel_mask;
+       const struct clksel     *clksel;
+       const struct dpll_data  *dpll_data;
+#else
+       __u8                    rate_offset;
+       __u8                    src_offset;
+#endif
 };
 
 struct clk_functions {
@@ -45,6 +86,10 @@ struct clk_functions {
        struct clk *    (*clk_get_parent)(struct clk *clk);
        void            (*clk_allow_idle)(struct clk *clk);
        void            (*clk_deny_idle)(struct clk *clk);
+       void            (*clk_disable_unused)(struct clk *clk);
+#ifdef CONFIG_CPU_FREQ
+       void            (*clk_init_cpufreq_table)(struct cpufreq_frequency_table **table);
+#endif
 };
 
 extern unsigned int mpurate;
@@ -53,10 +98,15 @@ extern int clk_init(struct clk_functions * custom_clocks);
 extern int clk_register(struct clk *clk);
 extern void clk_unregister(struct clk *clk);
 extern void propagate_rate(struct clk *clk);
+extern void recalculate_root_clocks(void);
 extern void followparent_recalc(struct clk * clk);
 extern void clk_allow_idle(struct clk *clk);
 extern void clk_deny_idle(struct clk *clk);
 extern int clk_get_usecount(struct clk *clk);
+extern void clk_enable_init_clocks(void);
+#ifdef CONFIG_CPU_FREQ
+extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+#endif
 
 /* Clock flags */
 #define RATE_CKCTL             (1 << 0)        /* Main fixed ratio clocks */
@@ -70,21 +120,29 @@ extern int clk_get_usecount(struct clk *clk);
 #define CLOCK_NO_IDLE_PARENT   (1 << 8)
 #define DELAYED_APP            (1 << 9)        /* Delay application of clock */
 #define CONFIG_PARTICIPANT     (1 << 10)       /* Fundamental clock */
-#define CM_MPU_SEL1            (1 << 11)       /* Domain divider/source */
-#define CM_DSP_SEL1            (1 << 12)
-#define CM_GFX_SEL1            (1 << 13)
-#define CM_MODEM_SEL1          (1 << 14)
-#define CM_CORE_SEL1           (1 << 15)       /* Sets divider for many */
-#define CM_CORE_SEL2           (1 << 16)       /* sets parent for GPT */
-#define CM_WKUP_SEL1           (1 << 17)
-#define CM_PLL_SEL1            (1 << 18)
-#define CM_PLL_SEL2            (1 << 19)
-#define CM_SYSCLKOUT_SEL1      (1 << 20)
+#define ENABLE_ON_INIT         (1 << 11)       /* Enable upon framework init */
+#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
+/* bits 13-20 are currently free */
 #define CLOCK_IN_OMAP310       (1 << 21)
 #define CLOCK_IN_OMAP730       (1 << 22)
 #define CLOCK_IN_OMAP1510      (1 << 23)
 #define CLOCK_IN_OMAP16XX      (1 << 24)
 #define CLOCK_IN_OMAP242X      (1 << 25)
 #define CLOCK_IN_OMAP243X      (1 << 26)
+#define CLOCK_IN_OMAP343X      (1 << 27)
+#define PARENT_CONTROLS_CLOCK  (1 << 28)
+
+/* Clksel_rate flags */
+#define DEFAULT_RATE            (1 << 0)
+#define RATE_IN_242X            (1 << 1)
+#define RATE_IN_243X            (1 << 2)
+#define RATE_IN_343X            (1 << 3)
+#define RATE_IN_24XX            (RATE_IN_242X | RATE_IN_243X)
+
+
+/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
+#define CORE_CLK_SRC_32K               0
+#define CORE_CLK_SRC_DPLL              1
+#define CORE_CLK_SRC_DPLL_X2           2
 
 #endif