[ARM] 4902/1: [AT91] SAM9/CAP9 memory controller header

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-at91 / at91sam9_sdramc.h

diff --git a/include/asm-arm/arch-at91/at91sam926x_mc.h b/include/asm-arm/arch-at91/at91sam9_sdramc.h
similarity index 52%
rename from include/asm-arm/arch-at91/at91sam926x_mc.h
rename to include/asm-arm/arch-at91/at91sam9_sdramc.h
index d82631c251f1b14af7eb2638be5b3652aec12188..d3b8b3da6b4d783030990eb2fede7ab892e89d36 100644 (file)
--- a/include/asm-arm/arch-at91/at91sam926x_mc.h
+++ b/include/asm-arm/arch-at91/at91sam9_sdramc.h
@@ -1,7 +1,7 @@
 /*
- * include/asm-arm/arch-at91/at91sam926x_mc.h
+ * include/asm-arm/arch-at91/at91sam9_sdramc.h
  *
- * Memory Controllers (SMC, SDRAMC) - System peripherals registers.
+ * SDRAM Controllers (SDRAMC) - System peripherals registers.
  * Based on AT91SAM9261 datasheet revision D.
  *
  * This program is free software; you can redistribute it and/or modify
@@ -10,8 +10,8 @@
  * (at your option) any later version.
  */
 
-#ifndef AT91SAM926x_MC_H
-#define AT91SAM926x_MC_H
+#ifndef AT91SAM9_SDRAMC_H
+#define AT91SAM9_SDRAMC_H
 
 /* SDRAM Controller (SDRAMC) registers */
 #define AT91_SDRAMC_MR         (AT91_SDRAMC + 0x00)    /* SDRAM Controller Mode Register */
@@ -62,7 +62,7 @@
 #define                        AT91_SDRAMC_LPCB_DEEP_POWER_DOWN        3
 #define                AT91_SDRAMC_PASR                (7 << 4)        /* Partial Array Self Refresh */
 #define                AT91_SDRAMC_TCSR                (3 << 8)        /* Temperature Compensated Self Refresh */
-#define                AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strenght */
+#define                AT91_SDRAMC_DS                  (3 << 10)       /* Drive Strength */
 #define                AT91_SDRAMC_TIMEOUT             (3 << 12)       /* Time to define when Low Power Mode is enabled */
 #define                        AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES        (0 << 12)
 #define                        AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES       (1 << 12)
@@ -80,62 +80,4 @@
 #define                        AT91_SDRAMC_MD_LOW_POWER_SDRAM  1
 
 
-/* Static Memory Controller (SMC) registers */
-#define AT91_SMC_SETUP(n)      (AT91_SMC + 0x00 + ((n)*0x10))  /* Setup Register for CS n */
-#define                AT91_SMC_NWESETUP       (0x3f << 0)                     /* NWE Setup Length */
-#define                        AT91_SMC_NWESETUP_(x)   ((x) << 0)
-#define                AT91_SMC_NCS_WRSETUP    (0x3f << 8)                     /* NCS Setup Length in Write Access */
-#define                        AT91_SMC_NCS_WRSETUP_(x)        ((x) << 8)
-#define                AT91_SMC_NRDSETUP       (0x3f << 16)                    /* NRD Setup Length */
-#define                        AT91_SMC_NRDSETUP_(x)   ((x) << 16)
-#define                AT91_SMC_NCS_RDSETUP    (0x3f << 24)                    /* NCS Setup Length in Read Access */
-#define                        AT91_SMC_NCS_RDSETUP_(x)        ((x) << 24)
-
-#define AT91_SMC_PULSE(n)      (AT91_SMC + 0x04 + ((n)*0x10))  /* Pulse Register for CS n */
-#define                AT91_SMC_NWEPULSE       (0x7f <<  0)                    /* NWE Pulse Length */
-#define                        AT91_SMC_NWEPULSE_(x)   ((x) << 0)
-#define                AT91_SMC_NCS_WRPULSE    (0x7f <<  8)                    /* NCS Pulse Length in Write Access */
-#define                        AT91_SMC_NCS_WRPULSE_(x)((x) << 8)
-#define                AT91_SMC_NRDPULSE       (0x7f << 16)                    /* NRD Pulse Length */
-#define                        AT91_SMC_NRDPULSE_(x)   ((x) << 16)
-#define                AT91_SMC_NCS_RDPULSE    (0x7f << 24)                    /* NCS Pulse Length in Read Access */
-#define                        AT91_SMC_NCS_RDPULSE_(x)((x) << 24)
-
-#define AT91_SMC_CYCLE(n)      (AT91_SMC + 0x08 + ((n)*0x10))  /* Cycle Register for CS n */
-#define                AT91_SMC_NWECYCLE       (0x1ff << 0 )                   /* Total Write Cycle Length */
-#define                        AT91_SMC_NWECYCLE_(x)   ((x) << 0)
-#define                AT91_SMC_NRDCYCLE       (0x1ff << 16)                   /* Total Read Cycle Length */
-#define                        AT91_SMC_NRDCYCLE_(x)   ((x) << 16)
-
-#define AT91_SMC_MODE(n)       (AT91_SMC + 0x0c + ((n)*0x10))  /* Mode Register for CS n */
-#define                AT91_SMC_READMODE       (1 <<  0)                       /* Read Mode */
-#define                AT91_SMC_WRITEMODE      (1 <<  1)                       /* Write Mode */
-#define                AT91_SMC_EXNWMODE       (3 <<  4)                       /* NWAIT Mode */
-#define                        AT91_SMC_EXNWMODE_DISABLE       (0 << 4)
-#define                        AT91_SMC_EXNWMODE_FROZEN        (2 << 4)
-#define                        AT91_SMC_EXNWMODE_READY         (3 << 4)
-#define                AT91_SMC_BAT            (1 <<  8)                       /* Byte Access Type */
-#define                        AT91_SMC_BAT_SELECT             (0 << 8)
-#define                        AT91_SMC_BAT_WRITE              (1 << 8)
-#define                AT91_SMC_DBW            (3 << 12)                       /* Data Bus Width */
-#define                        AT91_SMC_DBW_8                  (0 << 12)
-#define                        AT91_SMC_DBW_16                 (1 << 12)
-#define                        AT91_SMC_DBW_32                 (2 << 12)
-#define                AT91_SMC_TDF            (0xf << 16)                     /* Data Float Time. */
-#define                        AT91_SMC_TDF_(x)                ((x) << 16)
-#define                AT91_SMC_TDFMODE        (1 << 20)                       /* TDF Optimization - Enabled */
-#define                AT91_SMC_PMEN           (1 << 24)                       /* Page Mode Enabled */
-#define                AT91_SMC_PS             (3 << 28)                       /* Page Size */
-#define                        AT91_SMC_PS_4                   (0 << 28)
-#define                        AT91_SMC_PS_8                   (1 << 28)
-#define                        AT91_SMC_PS_16                  (2 << 28)
-#define                        AT91_SMC_PS_32                  (3 << 28)
-
-#if defined(AT91_SMC1)         /* The AT91SAM9263 has 2 Static Memory contollers */
-#define AT91_SMC1_SETUP(n)     (AT91_SMC1 + 0x00 + ((n)*0x10)) /* Setup Register for CS n */
-#define AT91_SMC1_PULSE(n)     (AT91_SMC1 + 0x04 + ((n)*0x10)) /* Pulse Register for CS n */
-#define AT91_SMC1_CYCLE(n)     (AT91_SMC1 + 0x08 + ((n)*0x10)) /* Cycle Register for CS n */
-#define AT91_SMC1_MODE(n)      (AT91_SMC1 + 0x0c + ((n)*0x10)) /* Mode Register for CS n */
-#endif
-
 #endif