[ARM] 4764/1: [AT91] AT91CAP9 core support

[linux-2.6-omap-h63xx.git] / include / asm-arm / arch-at91 / at91_pmc.h

diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 34804eaab4f26752373aa602b2e10f05554a480b..52cd8e5dabc996823368b60797e4a43d6764ec1d 100644 (file)
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -25,6 +25,7 @@
 #define                AT91RM9200_PMC_MCKUDP   (1 <<  2)               /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
 #define                AT91RM9200_PMC_UHP      (1 <<  4)               /* USB Host Port Clock [AT91RM9200 only] */
 #define                AT91SAM926x_PMC_UHP     (1 <<  6)               /* USB Host Port Clock [AT91SAM926x only] */
+#define                AT91CAP9_PMC_UHP        (1 <<  6)               /* USB Host Port Clock [AT91CAP9 only] */
 #define                AT91SAM926x_PMC_UDP     (1 <<  7)               /* USB Devcice Port Clock [AT91SAM926x only] */
 #define                AT91_PMC_PCK0           (1 <<  8)               /* Programmable Clock 0 */
 #define                AT91_PMC_PCK1           (1 <<  9)               /* Programmable Clock 1 */
@@ -37,7 +38,7 @@
 #define        AT91_PMC_PCDR           (AT91_PMC + 0x14)       /* Peripheral Clock Disable Register */
 #define        AT91_PMC_PCSR           (AT91_PMC + 0x18)       /* Peripheral Clock Status Register */
 
-#define        AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL only] */
+#define        AT91_CKGR_UCKR          (AT91_PMC + 0x1C)       /* UTMI Clock Register [SAM9RL, CAP9] */
 
 #define        AT91_CKGR_MOR           (AT91_PMC + 0x20)       /* Main Oscillator Register [not on SAM9RL] */
 #define                AT91_PMC_MOSCEN         (1    << 0)             /* Main Oscillator Enable */
@@ -54,6 +55,10 @@
 #define                AT91_PMC_PLLCOUNT       (0x3f  <<  8)           /* PLL Counter */
 #define                AT91_PMC_OUT            (3     << 14)           /* PLL Clock Frequency Range */
 #define                AT91_PMC_MUL            (0x7ff << 16)           /* PLL Multiplier */
+#define                AT91_PMC_USBDIV         (3     << 28)           /* USB Divisor (PLLB only) */
+#define                        AT91_PMC_USBDIV_1               (0 << 28)
+#define                        AT91_PMC_USBDIV_2               (1 << 28)
+#define                        AT91_PMC_USBDIV_4               (2 << 28)
 #define                AT91_PMC_USB96M         (1     << 28)           /* Divider by 2 Enable (PLLB only) */
 
 #define        AT91_PMC_MCKR           (AT91_PMC + 0x30)       /* Master Clock Register */