/*
- * File: drivers/video/omap_new/omapfb_main.c
+ * File: drivers/video/omap/omap1/sossi.c
*
- * Special optimiSed Screen Interface driver for TI OMAP boards
+ * OMAP1 Special OptimiSed Screen Interface support
*
- * Copyright (C) 2004 Nokia Corporation
+ * Copyright (C) 2004-2005 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
*
* This program is free software; you can redistribute it and/or modify it
#include <linux/config.h>
#include <linux/module.h>
#include <linux/mm.h>
+#include <linux/clk.h>
+
#include <asm/io.h>
-#include "sossi.h"
+#include <asm/arch/dma.h>
+#include <asm/arch/omapfb.h>
+
+#include "lcdc.h"
+
+/* #define OMAPFB_DBG 1 */
+
+#include "debug.h"
+
+#define MODULE_NAME "omapfb-sossi"
#define OMAP_SOSSI_BASE 0xfffbac00
#define SOSSI_ID_REG 0x00
#define DMA_LCD_CTRL 0xfffee3c4
#define DMA_LCD_LCH_CTRL 0xfffee3ea
-static int sossi_base = IO_ADDRESS(OMAP_SOSSI_BASE);
+#define RD_ACCESS 0
+#define WR_ACCESS 1
+
+#define SOSSI_MAX_XMIT_BYTES (512 * 1024)
+
+#define pr_err(fmt, args...) printk(KERN_ERR MODULE_NAME ": " fmt, ## args)
+
+static struct sossi {
+ int base;
+ unsigned long dpll_khz;
+ int bus_pick_width;
+ void (*lcdc_callback)(void *data);
+ void *lcdc_callback_data;
+ /* timing for read and write access */
+ int clk_div;
+ u8 clk_tw0[2];
+ u8 clk_tw1[2];
+ /* if last_access is the same as current we don't have to change
+ * the timings
+ */
+ int last_access;
+} sossi;
+
+struct lcd_ctrl_extif sossi_extif;
static inline u32 sossi_read_reg(int reg)
{
- return readl(sossi_base + reg);
+ return readl(sossi.base + reg);
}
static inline u16 sossi_read_reg16(int reg)
{
- return readw(sossi_base + reg);
+ return readw(sossi.base + reg);
}
static inline u8 sossi_read_reg8(int reg)
{
- return readb(sossi_base + reg);
+ return readb(sossi.base + reg);
}
static inline void sossi_write_reg(int reg, u32 value)
{
- writel(value, sossi_base + reg);
+ writel(value, sossi.base + reg);
}
static inline void sossi_write_reg16(int reg, u16 value)
{
- writew(value, sossi_base + reg);
+ writew(value, sossi.base + reg);
}
static inline void sossi_write_reg8(int reg, u8 value)
{
- writeb(value, sossi_base + reg);
+ writeb(value, sossi.base + reg);
}
static void sossi_set_bits(int reg, u32 bits)
sossi_write_reg(reg, sossi_read_reg(reg) & ~bits);
}
-#if 1
-void sossi_dump(void)
-{
- printk(" INIT1: 0x%08x\n", sossi_read_reg(SOSSI_INIT1_REG));
- printk(" INIT2: 0x%08x\n", sossi_read_reg(SOSSI_INIT2_REG));
- printk(" INIT3: 0x%08x\n", sossi_read_reg(SOSSI_INIT3_REG));
- printk(" TEARING: 0x%08x\n", sossi_read_reg(SOSSI_TEARING_REG));
- printk(" INIT1B: 0x%08x\n", sossi_read_reg(SOSSI_INIT1B_REG));
-}
-#endif
-
-static void sossi_dma_init(void)
-{
- /* OMAP3.1 mapping disable */
- omap_writel(omap_readl(DMA_GSCR) | (1 << 3), DMA_GSCR);
- /* Logical channel type to b0100 */
- omap_writew(omap_readw(DMA_LCD_LCH_CTRL) | (1 << 2), DMA_LCD_LCH_CTRL);
- /* LCD_DMA dest port to 1 */
- omap_writew(omap_readw(DMA_LCD_CTRL) | (1 << 8), DMA_LCD_CTRL);
- /* LCD_CCR OMAP31 comp mode */
- omap_writew(omap_readw(DMA_LCD_CCR) | (1 << 10), DMA_LCD_CCR);
-}
-
#define MOD_CONF_CTRL_1 0xfffe1110
#define CONF_SOSSI_RESET_R (1 << 23)
#define CONF_MOD_SOSSI_CLK_EN_R (1 << 16)
-int sossi_init(void)
+static void sossi_dma_callback(void *data);
+
+static int sossi_init(void)
{
u32 l, k;
+ struct clk *dpll_clk;
+ int r;
+
+ sossi.base = IO_ADDRESS(OMAP_SOSSI_BASE);
+
+ dpll_clk = clk_get(NULL, "ck_dpll1");
+ if (IS_ERR(dpll_clk)) {
+ pr_err("can't get dpll1 clock\n");
+ return PTR_ERR(dpll_clk);
+ }
+
+ sossi.dpll_khz = clk_get_rate(dpll_clk) / 1000;
+ clk_put(dpll_clk);
+
+ sossi_extif.max_transmit_size = SOSSI_MAX_XMIT_BYTES;
/* Reset and enable the SoSSI module */
l = omap_readl(MOD_CONF_CTRL_1);
omap_writel(l, MOD_CONF_CTRL_1);
l |= CONF_MOD_SOSSI_CLK_EN_R;
- /* FIXME: Hardcode divide ratio 3 */
- l |= 2 << 17;
omap_writel(l, MOD_CONF_CTRL_1);
omap_writel(omap_readl(ARM_IDLECT2) | (1 << 11), ARM_IDLECT2);
omap_writel(omap_readl(ARM_IDLECT1) | (1 << 6), ARM_IDLECT1);
- sossi_dma_init();
-
l = sossi_read_reg(SOSSI_INIT2_REG);
/* Enable and reset the SoSSI block */
l |= (1 << 0) | (1 << 1);
sossi_write_reg(SOSSI_ID_REG, 0);
l = sossi_read_reg(SOSSI_ID_REG);
k = sossi_read_reg(SOSSI_ID_REG);
-
+
if (l != 0x55555555 || k != 0xaaaaaaaa) {
- printk(KERN_ERR "Invalid SoSSI sync pattern: %08x, %08x\n", l, k);
+ pr_err("Invalid SoSSI sync pattern: %08x, %08x\n", l, k);
return -ENODEV;
}
+
+ if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
+ pr_err("can't get LCDC IRQ\n");
+ return r;
+ }
+
l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
l = sossi_read_reg(SOSSI_ID_REG);
- printk(KERN_INFO "SoSSI rev. %d.%d initialized\n", l >> 16, l & 0xffff);
+ pr_info(KERN_INFO MODULE_NAME ": version %d.%d initialized\n",
+ l >> 16, l & 0xffff);
l = sossi_read_reg(SOSSI_INIT1_REG);
l |= (1 << 19); /* DMA_MODE */
return 0;
}
-static void set_timings(int tw0, int tw1)
+static void sossi_cleanup(void)
+{
+ omap_lcdc_free_dma_callback();
+}
+
+#define KHZ_TO_PS(x) (1000000000 / (x))
+
+static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
+{
+ *clk_period = KHZ_TO_PS(sossi.dpll_khz);
+ *max_clk_div = 8;
+}
+
+static u32 ps_to_sossi_ticks(u32 ps, int div)
+{
+ u32 clk_period = KHZ_TO_PS(sossi.dpll_khz) * div;
+ return (clk_period + ps - 1) / clk_period;
+}
+
+static int calc_rd_timings(struct extif_timings *t)
+{
+ u32 tw0, tw1;
+ int reon, reoff, recyc, actim;
+ int div = t->clk_div;
+
+ /* Make sure that after conversion it still holds that:
+ * reoff > reon, recyc >= reoff, actim > reon
+ */
+ reon = ps_to_sossi_ticks(t->re_on_time, div);
+ /* reon will be exactly one sossi tick */
+ if (reon > 1)
+ return -1;
+
+ reoff = ps_to_sossi_ticks(t->re_off_time, div);
+
+ if (reoff <= reon)
+ reoff = reon + 1;
+
+ tw0 = reoff - reon;
+ if (tw0 > 0x10)
+ return -1;
+
+ recyc = ps_to_sossi_ticks(t->re_cycle_time, div);
+ if (recyc <= reoff)
+ recyc = reoff + 1;
+
+ tw1 = recyc - reoff;
+ /* values less then 3 result in the SOSSI block resetting itself */
+ if (tw1 < 3)
+ tw1 = 3;
+ if (tw1 > 0x40)
+ return -1;
+
+ actim = ps_to_sossi_ticks(t->access_time, div);
+ if (actim < reoff)
+ actim++;
+ /* access time (data hold time) will be exactly one sossi
+ * tick
+ */
+ if (actim - reoff > 1)
+ return -1;
+
+ t->tim[0] = tw0 - 1;
+ t->tim[1] = tw1 - 1;
+
+ return 0;
+}
+
+static int calc_wr_timings(struct extif_timings *t)
+{
+ u32 tw0, tw1;
+ int weon, weoff, wecyc;
+ int div = t->clk_div;
+
+ /* Make sure that after conversion it still holds that:
+ * weoff > weon, wecyc >= weoff
+ */
+ weon = ps_to_sossi_ticks(t->we_on_time, div);
+ /* weon will be exactly one sossi tick */
+ if (weon > 1)
+ return -1;
+
+ weoff = ps_to_sossi_ticks(t->we_off_time, div);
+ if (weoff <= weon)
+ weoff = weon + 1;
+ tw0 = weoff - weon;
+ if (tw0 > 0x10)
+ return -1;
+
+ wecyc = ps_to_sossi_ticks(t->we_cycle_time, div);
+ if (wecyc <= weoff)
+ wecyc = weoff + 1;
+
+ tw1 = wecyc - weoff;
+ /* values less then 3 result in the SOSSI block resetting itself */
+ if (tw1 < 3)
+ tw1 = 3;
+ if (tw1 > 0x40)
+ return -1;
+
+ t->tim[2] = tw0 - 1;
+ t->tim[3] = tw1 - 1;
+
+ return 0;
+}
+
+static int sossi_convert_timings(struct extif_timings *t)
+{
+ int r = 0;
+ int div = t->clk_div;
+
+ t->converted = 0;
+
+ if (div <= 0 || div > 8)
+ return -1;
+
+ /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
+ if ((r = calc_rd_timings(t)) < 0)
+ return r;
+
+ if ((r = calc_wr_timings(t)) < 0)
+ return r;
+
+ t->tim[4] = div - 1;
+
+ t->converted = 1;
+
+ return 0;
+}
+
+static void sossi_set_timings(const struct extif_timings *t)
+{
+ BUG_ON(!t->converted);
+
+ sossi.clk_tw0[RD_ACCESS] = t->tim[0];
+ sossi.clk_tw1[RD_ACCESS] = t->tim[1];
+
+ sossi.clk_tw0[WR_ACCESS] = t->tim[2];
+ sossi.clk_tw1[WR_ACCESS] = t->tim[3];
+
+ sossi.clk_div = t->tim[4];
+}
+
+static void _set_timing(int div, int tw0, int tw1)
{
u32 l;
+ DBGPRINT(2, "Using TW0 = %d, TW1 = %d, div = %d\n",
+ tw0 + 1, tw1 + 1, div + 1);
+
+ l = omap_readl(MOD_CONF_CTRL_1);
+ l &= ~(7 << 17);
+ l |= div << 17;
+ omap_writel(l, MOD_CONF_CTRL_1);
+
l = sossi_read_reg(SOSSI_INIT1_REG);
l &= ~((0x0f << 20) | (0x3f << 24));
- l |= ((tw0 & 0x0f) << 20) | ((tw1 & 0x3f) << 24);
+ l |= (tw0 << 20) | (tw1 << 24);
sossi_write_reg(SOSSI_INIT1_REG, l);
}
-static struct sossi {
- int bus_pick_width;
-} sossi;
+static inline void set_timing(int access)
+{
+ if (access != sossi.last_access) {
+ sossi.last_access = access;
+ _set_timing(sossi.clk_div,
+ sossi.clk_tw0[access], sossi.clk_tw1[access]);
+ }
+}
-void sossi_set_xfer_params(int tw0, int tw1, int bus_pick_count, int bus_pick_width)
+static void sossi_set_bits_per_cycle(int bpc)
{
u32 l;
-
- set_timings(tw0, tw1);
+ int bus_pick_count, bus_pick_width;
+
+ DBGPRINT(2, "bits_per_cycle %d\n", bpc);
+ /* We set explicitly the the bus_pick_count as well, although
+ * with remapping/reordering disabled it will be calculated by HW
+ * as (32 / bus_pick_width).
+ */
+ switch (bpc) {
+ case 8:
+ bus_pick_count = 4;
+ bus_pick_width = 8;
+ break;
+ case 16:
+ bus_pick_count = 2;
+ bus_pick_width = 16;
+ break;
+ default:
+ BUG();
+ return;
+ }
+ l = sossi_read_reg(SOSSI_INIT3_REG);
sossi.bus_pick_width = bus_pick_width;
- l = ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
+ l &= ~0x3ff;
+ l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
sossi_write_reg(SOSSI_INIT3_REG, l);
}
-void sossi_start_transfer(void)
+static void sossi_start_transfer(void)
{
/* WE */
sossi_clear_bits(SOSSI_INIT2_REG, 1 << 4);
/* FIXME: locking? */
}
-void sossi_stop_transfer(void)
+static void sossi_stop_transfer(void)
{
/* WE */
sossi_set_bits(SOSSI_INIT2_REG, 1 << 4);
/* FIXME: locking? */
}
+static void wait_end_of_write(void)
+{
+ /* Before reading we must check if some writings are going on */
+ while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
+}
+
static void send_data(const void *data, unsigned int len)
{
while (len >= 4) {
static void set_cycles(unsigned int len)
{
- int nr_cycles = len / (sossi.bus_pick_width / 8);
+ unsigned long nr_cycles = len / (sossi.bus_pick_width / 8);
+
+ BUG_ON((nr_cycles - 1) & ~0x3ffff);
sossi_clear_bits(SOSSI_INIT1_REG, 0x3ffff);
sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
}
-void sossi_send_cmd(const void *data, unsigned int len)
+static void sossi_write_command(const void *data, unsigned int len)
{
+ set_timing(WR_ACCESS);
+ /* CMD#/DATA */
sossi_clear_bits(SOSSI_INIT1_REG, 1 << 18);
- set_cycles(len);
+ set_cycles(len);
+ sossi_start_transfer();
send_data(data, len);
+ sossi_stop_transfer();
+ wait_end_of_write();
}
-void sossi_send_data(const void *data, unsigned int len)
+static void sossi_write_data(const void *data, unsigned int len)
{
+ set_timing(WR_ACCESS);
+ /* CMD#/DATA */
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
- set_cycles(len);
+ set_cycles(len);
+ sossi_start_transfer();
send_data(data, len);
+ sossi_stop_transfer();
+ wait_end_of_write();
}
-void sossi_prepare_dma_transfer(unsigned int count)
+static void sossi_transfer_area(int width, int height,
+ void (callback)(void *data), void *data)
{
- sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
- set_cycles(count);
-}
+ BUG_ON(callback == NULL);
-void sossi_send_data_const32(u32 data, unsigned int count)
-{
+ sossi.lcdc_callback = callback;
+ sossi.lcdc_callback_data = data;
+
+ set_timing(WR_ACCESS);
+ /* CMD#/DATA */
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
- set_cycles(count * 4);
- while (count > 0) {
- sossi_write_reg(SOSSI_FIFO_REG, data);
- count--;
- }
+ set_cycles(width * height * sossi.bus_pick_width / 8);
+
+ DBGPRINT(2, "SOSSI_INIT1_REG %08x\n", sossi_read_reg(SOSSI_INIT1_REG));
+
+ sossi_start_transfer();
+ omap_enable_lcd_dma();
}
-void sossi_set_tearing(int mode, int hs_counter, int detect_limit,
- int vs_counter, int vs_detect_limit, int flags)
+static void sossi_dma_callback(void *data)
{
- u32 l = 0;
-
- l |= vs_counter << 30;
- if (flags & SOSSI_FLAG_HS_INVERTED)
- l |= 1 << 29;
- if (flags & SOSSI_FLAG_VS_INVERTED)
- l |= 1 << 28;
- l |= mode << 26;
- l |= hs_counter << 15;
- l |= vs_detect_limit << 3;
- l |= detect_limit;
- sossi_write_reg(SOSSI_TEARING_REG, l);
+ omap_stop_lcd_dma();
+ sossi_stop_transfer();
+ sossi.lcdc_callback(sossi.lcdc_callback_data);
}
-void sossi_read_data(void *data, unsigned int len)
+static void sossi_read_data(void *data, unsigned int len)
{
- /* Before reading we must check if some writings are going on */
- while (!(sossi_read_reg(SOSSI_INIT2_REG) & (1 << 3)));
+ set_timing(RD_ACCESS);
+ /* CMD#/DATA */
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
- set_cycles(len);
+ set_cycles(len);
+ sossi_start_transfer();
while (len >= 4) {
*(u32 *) data = sossi_read_reg(SOSSI_FIFO_REG);
len -= 4;
len--;
data++;
}
+ sossi_stop_transfer();
}
+
+struct lcd_ctrl_extif sossi_extif = {
+ .init = sossi_init,
+ .cleanup = sossi_cleanup,
+ .get_clk_info = sossi_get_clk_info,
+ .convert_timings = sossi_convert_timings,
+ .set_timings = sossi_set_timings,
+ .set_bits_per_cycle = sossi_set_bits_per_cycle,
+ .write_command = sossi_write_command,
+ .read_data = sossi_read_data,
+ .write_data = sossi_write_data,
+ .transfer_area = sossi_transfer_area,
+};
projects / linux-2.6-omap-h63xx.git / blobdiff