* with this program; if not, write to the Free Software Foundation, Inc.,
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
-
#include <linux/config.h>
#include <linux/module.h>
#include <linux/mm.h>
#include "lcdc.h"
-/* #define OMAPFB_DBG 1 */
-
-#include "debug.h"
-
#define MODULE_NAME "omapfb-sossi"
#define OMAP_SOSSI_BASE 0xfffbac00
#define SOSSI_MAX_XMIT_BYTES (512 * 1024)
-#define pr_err(fmt, args...) printk(KERN_ERR MODULE_NAME ": " fmt, ## args)
-
-static struct sossi {
- int base;
+static struct {
+ void __iomem *base;
unsigned long dpll_khz;
int bus_pick_width;
void (*lcdc_callback)(void *data);
* the timings
*/
int last_access;
-} sossi;
-struct lcd_ctrl_extif sossi_extif;
+ struct omapfb_device *fbdev;
+ struct lcd_ctrl_extif *extif;
+} sossi;
static inline u32 sossi_read_reg(int reg)
{
static void sossi_dma_callback(void *data);
-static int sossi_init(void)
-{
- u32 l, k;
- struct clk *dpll_clk;
- int r;
-
- sossi.base = IO_ADDRESS(OMAP_SOSSI_BASE);
-
- dpll_clk = clk_get(NULL, "ck_dpll1");
- if (IS_ERR(dpll_clk)) {
- pr_err("can't get dpll1 clock\n");
- return PTR_ERR(dpll_clk);
- }
-
- sossi.dpll_khz = clk_get_rate(dpll_clk) / 1000;
- clk_put(dpll_clk);
-
- sossi_extif.max_transmit_size = SOSSI_MAX_XMIT_BYTES;
-
- /* Reset and enable the SoSSI module */
- l = omap_readl(MOD_CONF_CTRL_1);
- l |= CONF_SOSSI_RESET_R;
- omap_writel(l, MOD_CONF_CTRL_1);
- l &= ~CONF_SOSSI_RESET_R;
- omap_writel(l, MOD_CONF_CTRL_1);
-
- l |= CONF_MOD_SOSSI_CLK_EN_R;
- omap_writel(l, MOD_CONF_CTRL_1);
-
- omap_writel(omap_readl(ARM_IDLECT2) | (1 << 11), ARM_IDLECT2);
- omap_writel(omap_readl(ARM_IDLECT1) | (1 << 6), ARM_IDLECT1);
-
- l = sossi_read_reg(SOSSI_INIT2_REG);
- /* Enable and reset the SoSSI block */
- l |= (1 << 0) | (1 << 1);
- sossi_write_reg(SOSSI_INIT2_REG, l);
- /* Take SoSSI out of reset */
- l &= ~(1 << 1);
- sossi_write_reg(SOSSI_INIT2_REG, l);
-
- sossi_write_reg(SOSSI_ID_REG, 0);
- l = sossi_read_reg(SOSSI_ID_REG);
- k = sossi_read_reg(SOSSI_ID_REG);
-
- if (l != 0x55555555 || k != 0xaaaaaaaa) {
- pr_err("Invalid SoSSI sync pattern: %08x, %08x\n", l, k);
- return -ENODEV;
- }
-
- if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
- pr_err("can't get LCDC IRQ\n");
- return r;
- }
-
- l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
- l = sossi_read_reg(SOSSI_ID_REG);
- pr_info(KERN_INFO MODULE_NAME ": version %d.%d initialized\n",
- l >> 16, l & 0xffff);
-
- l = sossi_read_reg(SOSSI_INIT1_REG);
- l |= (1 << 19); /* DMA_MODE */
- l &= ~(1 << 31); /* REORDERING */
- sossi_write_reg(SOSSI_INIT1_REG, l);
-
- return 0;
-}
-
-static void sossi_cleanup(void)
-{
- omap_lcdc_free_dma_callback();
-}
-
#define KHZ_TO_PS(x) (1000000000 / (x))
-static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
-{
- *clk_period = KHZ_TO_PS(sossi.dpll_khz);
- *max_clk_div = 8;
-}
-
static u32 ps_to_sossi_ticks(u32 ps, int div)
{
u32 clk_period = KHZ_TO_PS(sossi.dpll_khz) * div;
return 0;
}
-static int sossi_convert_timings(struct extif_timings *t)
-{
- int r = 0;
- int div = t->clk_div;
-
- t->converted = 0;
-
- if (div <= 0 || div > 8)
- return -1;
-
- /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
- if ((r = calc_rd_timings(t)) < 0)
- return r;
-
- if ((r = calc_wr_timings(t)) < 0)
- return r;
-
- t->tim[4] = div - 1;
-
- t->converted = 1;
-
- return 0;
-}
-
-static void sossi_set_timings(const struct extif_timings *t)
-{
- BUG_ON(!t->converted);
-
- sossi.clk_tw0[RD_ACCESS] = t->tim[0];
- sossi.clk_tw1[RD_ACCESS] = t->tim[1];
-
- sossi.clk_tw0[WR_ACCESS] = t->tim[2];
- sossi.clk_tw1[WR_ACCESS] = t->tim[3];
-
- sossi.clk_div = t->tim[4];
-}
-
static void _set_timing(int div, int tw0, int tw1)
{
u32 l;
- DBGPRINT(2, "Using TW0 = %d, TW1 = %d, div = %d\n",
+#ifdef VERBOSE
+ dev_dbg(sossi.fbdev->dev, "Using TW0 = %d, TW1 = %d, div = %d\n",
tw0 + 1, tw1 + 1, div + 1);
+#endif
l = omap_readl(MOD_CONF_CTRL_1);
l &= ~(7 << 17);
}
}
-static void sossi_set_bits_per_cycle(int bpc)
-{
- u32 l;
- int bus_pick_count, bus_pick_width;
-
- DBGPRINT(2, "bits_per_cycle %d\n", bpc);
- /* We set explicitly the the bus_pick_count as well, although
- * with remapping/reordering disabled it will be calculated by HW
- * as (32 / bus_pick_width).
- */
- switch (bpc) {
- case 8:
- bus_pick_count = 4;
- bus_pick_width = 8;
- break;
- case 16:
- bus_pick_count = 2;
- bus_pick_width = 16;
- break;
- default:
- BUG();
- return;
- }
- l = sossi_read_reg(SOSSI_INIT3_REG);
- sossi.bus_pick_width = bus_pick_width;
- l &= ~0x3ff;
- l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
- sossi_write_reg(SOSSI_INIT3_REG, l);
-}
-
static void sossi_start_transfer(void)
{
/* WE */
sossi_set_bits(SOSSI_INIT1_REG, (nr_cycles - 1) & 0x3ffff);
}
+static int sossi_convert_timings(struct extif_timings *t)
+{
+ int r = 0;
+ int div = t->clk_div;
+
+ t->converted = 0;
+
+ if (div <= 0 || div > 8)
+ return -1;
+
+ /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */
+ if ((r = calc_rd_timings(t)) < 0)
+ return r;
+
+ if ((r = calc_wr_timings(t)) < 0)
+ return r;
+
+ t->tim[4] = div - 1;
+
+ t->converted = 1;
+
+ return 0;
+}
+
+static void sossi_set_timings(const struct extif_timings *t)
+{
+ BUG_ON(!t->converted);
+
+ sossi.clk_tw0[RD_ACCESS] = t->tim[0];
+ sossi.clk_tw1[RD_ACCESS] = t->tim[1];
+
+ sossi.clk_tw0[WR_ACCESS] = t->tim[2];
+ sossi.clk_tw1[WR_ACCESS] = t->tim[3];
+
+ sossi.clk_div = t->tim[4];
+}
+
+static void sossi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
+{
+ *clk_period = KHZ_TO_PS(sossi.dpll_khz);
+ *max_clk_div = 8;
+}
+
+static void sossi_set_bits_per_cycle(int bpc)
+{
+ u32 l;
+ int bus_pick_count, bus_pick_width;
+
+ /* We set explicitly the the bus_pick_count as well, although
+ * with remapping/reordering disabled it will be calculated by HW
+ * as (32 / bus_pick_width).
+ */
+ switch (bpc) {
+ case 8:
+ bus_pick_count = 4;
+ bus_pick_width = 8;
+ break;
+ case 16:
+ bus_pick_count = 2;
+ bus_pick_width = 16;
+ break;
+ default:
+ BUG();
+ return;
+ }
+ l = sossi_read_reg(SOSSI_INIT3_REG);
+ sossi.bus_pick_width = bus_pick_width;
+ l &= ~0x3ff;
+ l |= ((bus_pick_count - 1) << 5) | ((bus_pick_width - 1) & 0x1f);
+ sossi_write_reg(SOSSI_INIT3_REG, l);
+}
+
static void sossi_write_command(const void *data, unsigned int len)
{
set_timing(WR_ACCESS);
sossi_set_bits(SOSSI_INIT1_REG, 1 << 18);
set_cycles(width * height * sossi.bus_pick_width / 8);
- DBGPRINT(2, "SOSSI_INIT1_REG %08x\n", sossi_read_reg(SOSSI_INIT1_REG));
-
sossi_start_transfer();
omap_enable_lcd_dma();
}
sossi_stop_transfer();
}
-struct lcd_ctrl_extif sossi_extif = {
+static int sossi_init(struct omapfb_device *fbdev)
+{
+ u32 l, k;
+ struct clk *dpll_clk;
+ int r;
+
+ sossi.fbdev = fbdev;
+
+ sossi.base = (void __iomem *)IO_ADDRESS(OMAP_SOSSI_BASE);
+ dpll_clk = clk_get(fbdev->dev, "ck_dpll1");
+ if (IS_ERR(dpll_clk)) {
+ dev_err(fbdev->dev, "can't get dpll1 clock\n");
+ return PTR_ERR(dpll_clk);
+ }
+
+ sossi.dpll_khz = clk_get_rate(dpll_clk) / 1000;
+ clk_put(dpll_clk);
+
+ /* Reset and enable the SoSSI module */
+ l = omap_readl(MOD_CONF_CTRL_1);
+ l |= CONF_SOSSI_RESET_R;
+ omap_writel(l, MOD_CONF_CTRL_1);
+ l &= ~CONF_SOSSI_RESET_R;
+ omap_writel(l, MOD_CONF_CTRL_1);
+
+ l |= CONF_MOD_SOSSI_CLK_EN_R;
+ omap_writel(l, MOD_CONF_CTRL_1);
+
+ omap_writel(omap_readl(ARM_IDLECT2) | (1 << 11), ARM_IDLECT2);
+ omap_writel(omap_readl(ARM_IDLECT1) | (1 << 6), ARM_IDLECT1);
+
+ l = sossi_read_reg(SOSSI_INIT2_REG);
+ /* Enable and reset the SoSSI block */
+ l |= (1 << 0) | (1 << 1);
+ sossi_write_reg(SOSSI_INIT2_REG, l);
+ /* Take SoSSI out of reset */
+ l &= ~(1 << 1);
+ sossi_write_reg(SOSSI_INIT2_REG, l);
+
+ sossi_write_reg(SOSSI_ID_REG, 0);
+ l = sossi_read_reg(SOSSI_ID_REG);
+ k = sossi_read_reg(SOSSI_ID_REG);
+
+ if (l != 0x55555555 || k != 0xaaaaaaaa) {
+ dev_err(fbdev->dev,
+ "invalid SoSSI sync pattern: %08x, %08x\n", l, k);
+ return -ENODEV;
+ }
+
+ if ((r = omap_lcdc_set_dma_callback(sossi_dma_callback, NULL)) < 0) {
+ dev_err(fbdev->dev, "can't get LCDC IRQ\n");
+ return r;
+ }
+
+ l = sossi_read_reg(SOSSI_ID_REG); /* Component code */
+ l = sossi_read_reg(SOSSI_ID_REG);
+ pr_info("omapfb: SoSSI version %d.%d initialized\n",
+ l >> 16, l & 0xffff);
+
+ l = sossi_read_reg(SOSSI_INIT1_REG);
+ l |= (1 << 19); /* DMA_MODE */
+ l &= ~(1 << 31); /* REORDERING */
+ sossi_write_reg(SOSSI_INIT1_REG, l);
+
+ return 0;
+}
+
+static void sossi_cleanup(void)
+{
+ omap_lcdc_free_dma_callback();
+}
+
+const struct lcd_ctrl_extif omap1_ext_if = {
.init = sossi_init,
.cleanup = sossi_cleanup,
.get_clk_info = sossi_get_clk_info,
.read_data = sossi_read_data,
.write_data = sossi_write_data,
.transfer_area = sossi_transfer_area,
+
+ .max_transmit_size = SOSSI_MAX_XMIT_BYTES,
};
+
projects / linux-2.6-omap-h63xx.git / blobdiff