* a_wait_vrise_tmout triggers VBUS_ERROR transitions
*/
musb_writeb(mbase, MUSB_DEVCTL, MUSB_DEVCTL_SESSION);
- musb->ep0_stage = MGC_END0_START;
+ musb->ep0_stage = MUSB_EP0_START;
musb->xceiv.state = OTG_STATE_A_IDLE;
MUSB_HST_MODE(musb);
musb_set_vbus(musb, 1);
musb->is_active = 1;
set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
- musb->ep0_stage = MGC_END0_START;
+ musb->ep0_stage = MUSB_EP0_START;
#ifdef CONFIG_USB_MUSB_OTG
/* flush endpoints when transitioning from Device Mode */
if (is_peripheral_active(musb)) {
// REVISIT HNP; just force disconnect
}
- musb->delay_port_power_off = FALSE;
- musb_writew(mbase, MUSB_INTRTXE, musb->wEndMask);
- musb_writew(mbase, MUSB_INTRRXE, musb->wEndMask & 0xfffe);
+ musb_writew(mbase, MUSB_INTRTXE, musb->epmask);
+ musb_writew(mbase, MUSB_INTRRXE, musb->epmask & 0xfffe);
musb_writeb(mbase, MUSB_INTRUSBE, 0xf7);
#endif
musb->port1_status &= ~(USB_PORT_STAT_LOW_SPEED
* only host sees babble; only peripheral sees bus reset.
*/
if (int_usb & MUSB_INTR_RESET) {
+#ifdef CONFIG_USB_MUSB_HDRC_HCD
if (devctl & MUSB_DEVCTL_HM) {
/*
* Looks like non-HS BABBLE can be ignored, but
ERR("Stopping host session because of babble\n");
musb_writeb(mbase, MUSB_DEVCTL, 0);
}
- } else {
+ } else
+#endif /* CONFIG_USB_MUSB_HDRC_HCD */
+ {
DBG(1, "BUS RESET\n");
musb_g_reset(musb);
void __iomem *mbase = musb->mregs;
struct musb_hw_ep *ep;
u8 epnum;
- u16 wFrame;
+ u16 frame;
DBG(6, "START_OF_FRAME\n");
handled = IRQ_HANDLED;
/* start any periodic Tx transfers waiting for current frame */
- wFrame = musb_readw(mbase, MUSB_FRAME);
+ frame = musb_readw(mbase, MUSB_FRAME);
ep = musb->endpoints;
for (epnum = 1; (epnum < musb->nr_endpoints)
- && (musb->wEndMask >= (1 << epnum));
+ && (musb->epmask >= (1 << epnum));
epnum++, ep++) {
// FIXME handle framecounter wraps (12 bits)
// eliminate duplicated StartUrb logic
- if (ep->dwWaitFrame >= wFrame) {
+ if (ep->dwWaitFrame >= frame) {
ep->dwWaitFrame = 0;
printk("SOF --> periodic TX%s on %d\n",
ep->tx_channel ? " DMA" : "",
handled = IRQ_HANDLED;
switch (musb->xceiv.state) {
+#ifdef CONFIG_USB_MUSB_OTG
case OTG_STATE_A_PERIPHERAL:
musb_hnp_stop(musb);
break;
+#endif
case OTG_STATE_B_PERIPHERAL:
musb_g_suspend(musb);
musb->is_active = is_otg_enabled(musb)
DBG(2, "<== devctl %02x\n", devctl);
/* Set INT enable registers, enable interrupts */
- musb_writew(regs, MUSB_INTRTXE, musb->wEndMask);
- musb_writew(regs, MUSB_INTRRXE, musb->wEndMask & 0xfffe);
+ musb_writew(regs, MUSB_INTRTXE, musb->epmask);
+ musb_writew(regs, MUSB_INTRRXE, musb->epmask & 0xfffe);
musb_writeb(regs, MUSB_INTRUSBE, 0xf7);
musb_writeb(regs, MUSB_TESTMODE, 0);
/* NOTE rx and tx endpoint irqs aren't managed separately,
* which happens to be ok
*/
- musb->wEndMask |= (1 << hw_ep->epnum);
+ musb->epmask |= (1 << hw_ep->epnum);
return offset + (maxpacket << ((c_size & MUSB_FIFOSZ_DPB) ? 1 : 0));
}
break;
}
musb->nr_endpoints++;
- musb->wEndMask |= (1 << epnum);
+ musb->epmask |= (1 << epnum);
hw_ep->max_packet_sz_tx = 1 << (reg & 0x0f);
/* Initialize MUSB (M)HDRC part of the USB hardware subsystem;
* configure endpoints, or take their config from silicon
*/
-static int __init musb_core_init(u16 wType, struct musb *musb)
+static int __init musb_core_init(u16 musb_type, struct musb *musb)
{
#ifdef MUSB_AHB_ID
- u32 dwData;
+ u32 data;
#endif
u8 reg;
char *type;
- u16 wRelease, wRelMajor, wRelMinor;
+ u16 hwvers, rev_major, rev_minor;
char aInfo[78], aRevision[32], aDate[12];
void __iomem *mbase = musb->mregs;
int status = 0;
musb_driver_name, reg, aInfo);
#ifdef MUSB_AHB_ID
- dwData = musb_readl(mbase, 0x404);
- sprintf(aDate, "%04d-%02x-%02x", (dwData & 0xffff),
- (dwData >> 16) & 0xff, (dwData >> 24) & 0xff);
+ data = musb_readl(mbase, 0x404);
+ sprintf(aDate, "%04d-%02x-%02x", (data & 0xffff),
+ (data >> 16) & 0xff, (data >> 24) & 0xff);
/* FIXME ID2 and ID3 are unused */
- dwData = musb_readl(mbase, 0x408);
- printk("ID2=%lx\n", (long unsigned)dwData);
- dwData = musb_readl(mbase, 0x40c);
- printk("ID3=%lx\n", (long unsigned)dwData);
+ data = musb_readl(mbase, 0x408);
+ printk("ID2=%lx\n", (long unsigned)data);
+ data = musb_readl(mbase, 0x40c);
+ printk("ID3=%lx\n", (long unsigned)data);
reg = musb_readb(mbase, 0x400);
- wType = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
+ musb_type = ('M' == reg) ? MUSB_CONTROLLER_MHDRC : MUSB_CONTROLLER_HDRC;
#else
aDate[0] = 0;
#endif
- if (MUSB_CONTROLLER_MHDRC == wType) {
+ if (MUSB_CONTROLLER_MHDRC == musb_type) {
musb->is_multipoint = 1;
type = "M";
} else {
}
/* log release info */
- wRelease = musb_readw(mbase, MUSB_HWVERS);
- wRelMajor = (wRelease >> 10) & 0x1f;
- wRelMinor = wRelease & 0x3ff;
- snprintf(aRevision, 32, "%d.%d%s", wRelMajor,
- wRelMinor, (wRelease & 0x8000) ? "RC" : "");
+ hwvers = musb_readw(mbase, MUSB_HWVERS);
+ rev_major = (hwvers >> 10) & 0x1f;
+ rev_minor = hwvers & 0x3ff;
+ snprintf(aRevision, 32, "%d.%d%s", rev_major,
+ rev_minor, (hwvers & 0x8000) ? "RC" : "");
printk(KERN_DEBUG "%s: %sHDRC RTL version %s %s\n",
musb_driver_name, type, aRevision, aDate);
/* discover endpoint configuration */
musb->nr_endpoints = 1;
- musb->wEndMask = 1;
+ musb->epmask = 1;
if (reg & MUSB_CONFIGDATA_DYNFIFO) {
if (can_dynfifo())
hw_ep->conf = mbase + 0x400 + (((i - 1) & 0xf) << 2);
#endif
- hw_ep->regs = MGC_END_OFFSET(i, 0) + mbase;
+ hw_ep->regs = MUSB_EP_OFFSET(i, 0) + mbase;
#ifdef CONFIG_USB_MUSB_HDRC_HCD
hw_ep->target_regs = MUSB_BUSCTL_OFFSET(i, 0) + mbase;
hw_ep->rx_reinit = 1;
const char *buf, size_t n)
{
struct musb *musb=dev_to_musb(dev);
- unsigned long flags;
unsigned short srp;
if (sscanf(buf, "%hu", &srp) != 1
return -EINVAL;
}
- spin_lock_irqsave(&musb->lock, flags);
if (srp == 1)
musb_g_wakeup(musb);
- spin_unlock_irqrestore(&musb->lock, flags);
return n;
}