case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
musb_hnp_stop(musb);
break;
+ case OTG_STATE_B_IDLE:
+ musb->xceiv.state = OTG_STATE_B_PERIPHERAL;
+ /* FALLTHROUGH */
case OTG_STATE_B_PERIPHERAL:
musb_g_reset(musb);
break;
unsigned long flags;
unsigned long val;
- spin_lock_irqsave(&musb->lock, flags);
if (sscanf(buf, "%lu", &val) < 1) {
printk(KERN_ERR "Invalid VBUS timeout ms value\n");
return -EINVAL;
}
+
+ spin_lock_irqsave(&musb->lock, flags);
musb->a_wait_bcon = val;
if (musb->xceiv.state == OTG_STATE_A_WAIT_BCON)
musb->is_active = 0;
ep->epnum = epnum;
}
+#ifdef CONFIG_USB_MUSB_OTG
+ otg_set_transceiver(&musb->xceiv);
+#endif
musb->controller = dev;
return musb;
}
clk_put(musb->clock);
}
+#ifdef CONFIG_USB_MUSB_OTG
+ put_device(musb->xceiv.dev);
+#endif
+
#ifdef CONFIG_USB_MUSB_HDRC_HCD
usb_put_hcd(musb_to_hcd(musb));
#else