if (ep->bEndpointAddress & USB_DIR_IN)
num |= UDC_EP_DIR;
- UDC_EP_NUM_REG = num | select;
+ omap_writew(num | select, UDC_EP_NUM);
/* when select, MUST deselect later !! */
}
static inline void deselect_ep(void)
{
- UDC_EP_NUM_REG &= ~UDC_EP_SEL;
+ u16 w;
+
+ w = omap_readw(UDC_EP_NUM);
+ w &= ~UDC_EP_SEL;
+ omap_writew(w, UDC_EP_NUM);
/* 6 wait states before TX will happen */
}
ep->has_dma = 0;
ep->lch = -1;
use_ep(ep, UDC_EP_SEL);
- UDC_CTRL_REG = udc->clr_halt;
+ omap_writew(udc->clr_halt, UDC_CTRL);
ep->ackwait = 0;
deselect_ep();
if (desc->bmAttributes != USB_ENDPOINT_XFER_ISOC
&& !ep->has_dma
&& !(ep->bEndpointAddress & USB_DIR_IN)) {
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
ep->ackwait = 1 + ep->double_buf;
}
nuke (ep, -ESHUTDOWN);
ep->ep.maxpacket = ep->maxpacket;
ep->has_dma = 0;
- UDC_CTRL_REG = UDC_SET_HALT;
+ omap_writew(UDC_SET_HALT, UDC_CTRL);
list_del_init(&ep->iso);
del_timer(&ep->timer);
if (likely((((int)buf) & 1) == 0)) {
wp = (u16 *)buf;
while (max >= 2) {
- UDC_DATA_REG = *wp++;
+ omap_writew(*wp++, UDC_DATA);
max -= 2;
}
buf = (u8 *)wp;
}
while (max--)
- *(volatile u8 *)&UDC_DATA_REG = *buf++;
+ omap_writeb(*buf++, UDC_DATA);
return len;
}
prefetch(buf);
/* PIO-IN isn't double buffered except for iso */
- ep_stat = UDC_STAT_FLG_REG;
+ ep_stat = omap_readw(UDC_STAT_FLG);
if (ep_stat & UDC_FIFO_UNWRITABLE)
return 0;
count = ep->ep.maxpacket;
count = write_packet(buf, req, count);
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
ep->ackwait = 1;
/* last packet is often short (sometimes a zlp) */
if (likely((((int)buf) & 1) == 0)) {
wp = (u16 *)buf;
while (avail >= 2) {
- *wp++ = UDC_DATA_REG;
+ *wp++ = omap_readw(UDC_DATA);
avail -= 2;
}
buf = (u8 *)wp;
}
while (avail--)
- *buf++ = *(volatile u8 *)&UDC_DATA_REG;
+ *buf++ = omap_readb(UDC_DATA);
return len;
}
prefetchw(buf);
for (;;) {
- u16 ep_stat = UDC_STAT_FLG_REG;
+ u16 ep_stat = omap_readw(UDC_STAT_FLG);
is_last = 0;
if (ep_stat & FIFO_EMPTY) {
if (ep_stat & UDC_FIFO_FULL)
avail = ep->ep.maxpacket;
else {
- avail = UDC_RXFSTAT_REG;
+ avail = omap_readw(UDC_RXFSTAT);
ep->fnf = ep->double_buf;
}
count = read_packet(buf, req, avail);
req->req.status = -EOVERFLOW;
avail -= count;
while (avail--)
- (void) *(volatile u8 *)&UDC_DATA_REG;
+ omap_readw(UDC_DATA);
}
} else if (req->req.length == req->req.actual)
is_last = 1;
static void next_in_dma(struct omap_ep *ep, struct omap_req *req)
{
- u16 txdma_ctrl;
+ u16 txdma_ctrl, w;
unsigned length = req->req.length - req->req.actual;
const int sync_mode = cpu_is_omap15xx()
? OMAP_DMA_SYNC_FRAME
omap_start_dma(ep->lch);
ep->dma_counter = omap_get_dma_src_pos(ep->lch);
- UDC_DMA_IRQ_EN_REG |= UDC_TX_DONE_IE(ep->dma_channel);
- UDC_TXDMA_REG(ep->dma_channel) = UDC_TXN_START | txdma_ctrl;
+ w = omap_readw(UDC_DMA_IRQ_EN);
+ w |= UDC_TX_DONE_IE(ep->dma_channel);
+ omap_writew(w, UDC_DMA_IRQ_EN);
+ omap_writew(UDC_TXN_START | txdma_ctrl, UDC_TXDMA(ep->dma_channel));
req->dma_bytes = length;
}
static void finish_in_dma(struct omap_ep *ep, struct omap_req *req, int status)
{
+ u16 w;
+
if (status == 0) {
req->req.actual += req->dma_bytes;
/* tx completion */
omap_stop_dma(ep->lch);
- UDC_DMA_IRQ_EN_REG &= ~UDC_TX_DONE_IE(ep->dma_channel);
+ w = omap_readw(UDC_DMA_IRQ_EN);
+ w &= ~UDC_TX_DONE_IE(ep->dma_channel);
+ omap_writew(w, UDC_DMA_IRQ_EN);
done(ep, req, status);
}
{
unsigned packets = req->req.length - req->req.actual;
int dma_trigger = 0;
+ u16 w;
if (cpu_is_omap24xx())
dma_trigger = OMAP24XX_DMA(USB_W2FC_RX0, ep->dma_channel);
0, 0);
ep->dma_counter = omap_get_dma_dst_pos(ep->lch);
- UDC_RXDMA_REG(ep->dma_channel) = UDC_RXN_STOP | (packets - 1);
- UDC_DMA_IRQ_EN_REG |= UDC_RX_EOT_IE(ep->dma_channel);
- UDC_EP_NUM_REG = (ep->bEndpointAddress & 0xf);
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(UDC_RXN_STOP | (packets - 1), UDC_RXDMA(ep->dma_channel));
+ w = omap_readw(UDC_DMA_IRQ_EN);
+ w |= UDC_RX_EOT_IE(ep->dma_channel);
+ omap_writew(w, UDC_DMA_IRQ_EN);
+ omap_writew(ep->bEndpointAddress & 0xf, UDC_EP_NUM);
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
omap_start_dma(ep->lch);
}
static void
finish_out_dma(struct omap_ep *ep, struct omap_req *req, int status, int one)
{
- u16 count;
+ u16 count, w;
if (status == 0)
ep->dma_counter = (u16) (req->req.dma + req->req.actual);
return;
/* rx completion */
- UDC_DMA_IRQ_EN_REG &= ~UDC_RX_EOT_IE(ep->dma_channel);
+ w = omap_readw(UDC_DMA_IRQ_EN);
+ w &= ~UDC_RX_EOT_IE(ep->dma_channel);
+ omap_writew(w, UDC_DMA_IRQ_EN);
done(ep, req, status);
}
static void dma_irq(struct omap_udc *udc, u16 irq_src)
{
- u16 dman_stat = UDC_DMAN_STAT_REG;
+ u16 dman_stat = omap_readw(UDC_DMAN_STAT);
struct omap_ep *ep;
struct omap_req *req;
struct omap_req, queue);
finish_in_dma(ep, req, 0);
}
- UDC_IRQ_SRC_REG = UDC_TXN_DONE;
+ omap_writew(UDC_TXN_DONE, UDC_IRQ_SRC);
if (!list_empty (&ep->queue)) {
req = container_of(ep->queue.next,
struct omap_req, queue);
finish_out_dma(ep, req, 0, dman_stat & UDC_DMA_RX_SB);
}
- UDC_IRQ_SRC_REG = UDC_RXN_EOT;
+ omap_writew(UDC_RXN_EOT, UDC_IRQ_SRC);
if (!list_empty (&ep->queue)) {
req = container_of(ep->queue.next,
ep->irqs++;
/* omap15xx does this unasked... */
VDBG("%s, RX_CNT irq?\n", ep->ep.name);
- UDC_IRQ_SRC_REG = UDC_RXN_CNT;
+ omap_writew(UDC_RXN_CNT, UDC_IRQ_SRC);
}
}
is_in = ep->bEndpointAddress & USB_DIR_IN;
if (is_in)
- reg = UDC_TXDMA_CFG_REG;
+ reg = omap_readw(UDC_TXDMA_CFG);
else
- reg = UDC_RXDMA_CFG_REG;
+ reg = omap_readw(UDC_RXDMA_CFG);
reg |= UDC_DMA_REQ; /* "pulse" activated */
ep->dma_channel = 0;
status = omap_request_dma(dma_channel,
ep->ep.name, dma_error, ep, &ep->lch);
if (status == 0) {
- UDC_TXDMA_CFG_REG = reg;
+ omap_writew(reg, UDC_TXDMA_CFG);
/* EMIFF or SDRC */
omap_set_dma_src_burst_mode(ep->lch,
OMAP_DMA_DATA_BURST_4);
omap_set_dma_dest_params(ep->lch,
OMAP_DMA_PORT_TIPB,
OMAP_DMA_AMODE_CONSTANT,
- (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
+ (unsigned long) io_v2p(UDC_DATA_DMA),
0, 0);
}
} else {
status = omap_request_dma(dma_channel,
ep->ep.name, dma_error, ep, &ep->lch);
if (status == 0) {
- UDC_RXDMA_CFG_REG = reg;
+ omap_writew(reg, UDC_RXDMA_CFG);
/* TIPB */
omap_set_dma_src_params(ep->lch,
OMAP_DMA_PORT_TIPB,
OMAP_DMA_AMODE_CONSTANT,
- (unsigned long) io_v2p((u32)&UDC_DATA_DMA_REG),
+ (unsigned long) io_v2p(UDC_DATA_DMA),
0, 0);
/* EMIFF or SDRC */
omap_set_dma_dest_burst_mode(ep->lch,
(is_in ? write_fifo : read_fifo)(ep, req);
deselect_ep();
if (!is_in) {
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
ep->ackwait = 1 + ep->double_buf;
}
/* IN: 6 wait states before it'll tx */
/* wait till current packet DMA finishes, and fifo empties */
if (ep->bEndpointAddress & USB_DIR_IN) {
- UDC_TXDMA_CFG_REG = (UDC_TXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
+ omap_writew((omap_readw(UDC_TXDMA_CFG) & ~mask) | UDC_DMA_REQ,
+ UDC_TXDMA_CFG);
if (req) {
finish_in_dma(ep, req, -ECONNRESET);
/* clear FIFO; hosts probably won't empty it */
use_ep(ep, UDC_EP_SEL);
- UDC_CTRL_REG = UDC_CLR_EP;
+ omap_writew(UDC_CLR_EP, UDC_CTRL);
deselect_ep();
}
- while (UDC_TXDMA_CFG_REG & mask)
+ while (omap_readw(UDC_TXDMA_CFG) & mask)
udelay(10);
} else {
- UDC_RXDMA_CFG_REG = (UDC_RXDMA_CFG_REG & ~mask) | UDC_DMA_REQ;
+ omap_writew((omap_readw(UDC_RXDMA_CFG) & ~mask) | UDC_DMA_REQ,
+ UDC_RXDMA_CFG);
/* dma empties the fifo */
- while (UDC_RXDMA_CFG_REG & mask)
+ while (omap_readw(UDC_RXDMA_CFG) & mask)
udelay(10);
if (req)
finish_out_dma(ep, req, -ECONNRESET, 0);
req->req.actual = 0;
/* maybe kickstart non-iso i/o queues */
- if (is_iso)
- UDC_IRQ_EN_REG |= UDC_SOF_IE;
- else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
+ if (is_iso) {
+ u16 w;
+
+ w = omap_readw(UDC_IRQ_EN);
+ w |= UDC_SOF_IE;
+ omap_writew(w, UDC_IRQ_EN);
+ } else if (list_empty(&ep->queue) && !ep->stopped && !ep->ackwait) {
int is_in;
if (ep->bEndpointAddress == 0) {
* requests to non-control endpoints
*/
if (udc->ep0_set_config) {
- u16 irq_en = UDC_IRQ_EN_REG;
+ u16 irq_en = omap_readw(UDC_IRQ_EN);
irq_en |= UDC_DS_CHG_IE | UDC_EP0_IE;
if (!udc->ep0_reset_config)
irq_en |= UDC_EPN_RX_IE
| UDC_EPN_TX_IE;
- UDC_IRQ_EN_REG = irq_en;
+ omap_writew(irq_en, UDC_IRQ_EN);
}
/* STATUS for zero length DATA stages is
* always an IN ... even for IN transfers,
* a weird case which seem to stall OMAP.
*/
- UDC_EP_NUM_REG = (UDC_EP_SEL|UDC_EP_DIR);
- UDC_CTRL_REG = UDC_CLR_EP;
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
- UDC_EP_NUM_REG = UDC_EP_DIR;
+ omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
+ omap_writew(UDC_CLR_EP, UDC_CTRL);
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+ omap_writew(UDC_EP_DIR, UDC_EP_NUM);
/* cleanup */
udc->ep0_pending = 0;
/* non-empty DATA stage */
} else if (is_in) {
- UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
+ omap_writew(UDC_EP_SEL | UDC_EP_DIR, UDC_EP_NUM);
} else {
if (udc->ep0_setup)
goto irq_wait;
- UDC_EP_NUM_REG = UDC_EP_SEL;
+ omap_writew(UDC_EP_SEL, UDC_EP_NUM);
}
} else {
is_in = ep->bEndpointAddress & USB_DIR_IN;
req = NULL;
deselect_ep();
if (!is_in) {
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
ep->ackwait = 1 + ep->double_buf;
}
/* IN: 6 wait states before it'll tx */
else if (value) {
if (ep->udc->ep0_set_config) {
WARN("error changing config?\n");
- UDC_SYSCON2_REG = UDC_CLR_CFG;
+ omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
}
- UDC_SYSCON2_REG = UDC_STALL_CMD;
+ omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
ep->udc->ep0_pending = 0;
status = 0;
} else /* NOP */
channel = 0;
use_ep(ep, UDC_EP_SEL);
- if (UDC_STAT_FLG_REG & UDC_NON_ISO_FIFO_EMPTY) {
- UDC_CTRL_REG = UDC_SET_HALT;
+ if (omap_readw(UDC_STAT_FLG) & UDC_NON_ISO_FIFO_EMPTY) {
+ omap_writew(UDC_SET_HALT, UDC_CTRL);
status = 0;
} else
status = -EAGAIN;
dma_channel_claim(ep, channel);
} else {
use_ep(ep, 0);
- UDC_CTRL_REG = ep->udc->clr_halt;
+ omap_writew(ep->udc->clr_halt, UDC_CTRL);
ep->ackwait = 0;
if (!(ep->bEndpointAddress & USB_DIR_IN)) {
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
ep->ackwait = 1 + ep->double_buf;
}
}
static int omap_get_frame(struct usb_gadget *gadget)
{
- u16 sof = UDC_SOF_REG;
+ u16 sof = omap_readw(UDC_SOF);
return (sof & UDC_TS_OK) ? (sof & UDC_TS) : -EL2NSYNC;
}
*/
if (udc->devstat & (UDC_B_HNP_ENABLE|UDC_R_WK_OK)) {
DBG("remote wakeup...\n");
- UDC_SYSCON2_REG = UDC_RMT_WKP;
+ omap_writew(UDC_RMT_WKP, UDC_SYSCON2);
retval = 0;
}
udc = container_of(gadget, struct omap_udc, gadget);
spin_lock_irqsave(&udc->lock, flags);
- syscon1 = UDC_SYSCON1_REG;
+ syscon1 = omap_readw(UDC_SYSCON1);
if (is_selfpowered)
syscon1 |= UDC_SELF_PWR;
else
syscon1 &= ~UDC_SELF_PWR;
- UDC_SYSCON1_REG = syscon1;
+ omap_writew(syscon1, UDC_SYSCON1);
spin_unlock_irqrestore(&udc->lock, flags);
return 0;
static void pullup_enable(struct omap_udc *udc)
{
- UDC_SYSCON1_REG |= UDC_PULLUP_EN;
- if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
- OTG_CTRL_REG |= OTG_BSESSVLD;
- UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
+ u16 w;
+
+ w = omap_readw(UDC_SYSCON1);
+ w |= UDC_PULLUP_EN;
+ omap_writew(w, UDC_SYSCON1);
+ if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
+ u32 l;
+
+ l = omap_readl(OTG_CTRL);
+ l |= OTG_BSESSVLD;
+ omap_writel(l, OTG_CTRL);
+ }
+ omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
}
static void pullup_disable(struct omap_udc *udc)
{
- if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx())
- OTG_CTRL_REG &= ~OTG_BSESSVLD;
- UDC_IRQ_EN_REG = UDC_DS_CHG_IE;
- UDC_SYSCON1_REG &= ~UDC_PULLUP_EN;
+ u16 w;
+
+ if (!gadget_is_otg(&udc->gadget) && !cpu_is_omap15xx()) {
+ u32 l;
+
+ l = omap_readl(OTG_CTRL);
+ l &= ~OTG_BSESSVLD;
+ omap_writel(l, OTG_CTRL);
+ }
+ omap_writew(UDC_DS_CHG_IE, UDC_IRQ_EN);
+ w = omap_readw(UDC_SYSCON1);
+ w &= ~UDC_PULLUP_EN;
+ omap_writew(w, UDC_SYSCON1);
}
static struct omap_udc *udc;
{
struct omap_udc *udc;
unsigned long flags;
+ u32 l;
udc = container_of(gadget, struct omap_udc, gadget);
spin_lock_irqsave(&udc->lock, flags);
udc->vbus_active = (is_active != 0);
if (cpu_is_omap15xx()) {
/* "software" detect, ignored if !VBUS_MODE_1510 */
+ l = omap_readl(FUNC_MUX_CTRL_0);
if (is_active)
- FUNC_MUX_CTRL_0_REG |= VBUS_CTRL_1510;
+ l |= VBUS_CTRL_1510;
else
- FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
+ l &= ~VBUS_CTRL_1510;
+ omap_writel(l, FUNC_MUX_CTRL_0);
}
if (udc->dc_clk != NULL && is_active) {
if (!udc->clk_requested) {
dma_channel_release(ep);
use_ep(ep, 0);
- UDC_CTRL_REG = UDC_CLR_EP;
+ omap_writew(UDC_CLR_EP, UDC_CTRL);
if (ep->bEndpointAddress && ep->bmAttributes != USB_ENDPOINT_XFER_ISOC)
- UDC_CTRL_REG = UDC_SET_HALT;
+ omap_writew(UDC_SET_HALT, UDC_CTRL);
while (!list_empty(&ep->queue)) {
req = list_entry(ep->queue.next, struct omap_req, queue);
if (!gadget_is_otg(&udc->gadget))
return;
- if (OTG_CTRL_REG & OTG_ID)
- devstat = UDC_DEVSTAT_REG;
+ if (omap_readl(OTG_CTRL) & OTG_ID)
+ devstat = omap_readw(UDC_DEVSTAT);
else
devstat = 0;
/* Enable HNP early, avoiding races on suspend irq path.
* ASSUMES OTG state machine B_BUS_REQ input is true.
*/
- if (udc->gadget.b_hnp_enable)
- OTG_CTRL_REG = (OTG_CTRL_REG | OTG_B_HNPEN | OTG_B_BUSREQ)
- & ~OTG_PULLUP;
+ if (udc->gadget.b_hnp_enable) {
+ u32 l;
+
+ l = omap_readl(OTG_CTRL);
+ l |= OTG_B_HNPEN | OTG_B_BUSREQ;
+ l &= ~OTG_PULLUP;
+ omap_writel(l, OTG_CTRL);
+ }
}
static void ep0_irq(struct omap_udc *udc, u16 irq_src)
nuke(ep0, 0);
if (ack) {
- UDC_IRQ_SRC_REG = ack;
+ omap_writew(ack, UDC_IRQ_SRC);
irq_src = UDC_SETUP;
}
}
if (irq_src & UDC_EP0_TX) {
int stat;
- UDC_IRQ_SRC_REG = UDC_EP0_TX;
- UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
- stat = UDC_STAT_FLG_REG;
+ omap_writew(UDC_EP0_TX, UDC_IRQ_SRC);
+ omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
+ stat = omap_readw(UDC_STAT_FLG);
if (stat & UDC_ACK) {
if (udc->ep0_in) {
/* write next IN packet from response,
*/
if (req)
stat = write_fifo(ep0, req);
- UDC_EP_NUM_REG = UDC_EP_DIR;
+ omap_writew(UDC_EP_DIR, UDC_EP_NUM);
if (!req && udc->ep0_pending) {
- UDC_EP_NUM_REG = UDC_EP_SEL;
- UDC_CTRL_REG = UDC_CLR_EP;
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
- UDC_EP_NUM_REG = 0;
+ omap_writew(UDC_EP_SEL, UDC_EP_NUM);
+ omap_writew(UDC_CLR_EP, UDC_CTRL);
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+ omap_writew(0, UDC_EP_NUM);
udc->ep0_pending = 0;
} /* else: 6 wait states before it'll tx */
} else {
/* ack status stage of OUT transfer */
- UDC_EP_NUM_REG = UDC_EP_DIR;
+ omap_writew(UDC_EP_DIR, UDC_EP_NUM);
if (req)
done(ep0, req, 0);
}
req = NULL;
} else if (stat & UDC_STALL) {
- UDC_CTRL_REG = UDC_CLR_HALT;
- UDC_EP_NUM_REG = UDC_EP_DIR;
+ omap_writew(UDC_CLR_HALT, UDC_CTRL);
+ omap_writew(UDC_EP_DIR, UDC_EP_NUM);
} else {
- UDC_EP_NUM_REG = UDC_EP_DIR;
+ omap_writew(UDC_EP_DIR, UDC_EP_NUM);
}
}
if (irq_src & UDC_EP0_RX) {
int stat;
- UDC_IRQ_SRC_REG = UDC_EP0_RX;
- UDC_EP_NUM_REG = UDC_EP_SEL;
- stat = UDC_STAT_FLG_REG;
+ omap_writew(UDC_EP0_RX, UDC_IRQ_SRC);
+ omap_writew(UDC_EP_SEL, UDC_EP_NUM);
+ stat = omap_readw(UDC_STAT_FLG);
if (stat & UDC_ACK) {
if (!udc->ep0_in) {
stat = 0;
* reactiviting the fifo; stall on errors.
*/
if (!req || (stat = read_fifo(ep0, req)) < 0) {
- UDC_SYSCON2_REG = UDC_STALL_CMD;
+ omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
udc->ep0_pending = 0;
stat = 0;
} else if (stat == 0)
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
- UDC_EP_NUM_REG = 0;
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+ omap_writew(0, UDC_EP_NUM);
/* activate status stage */
if (stat == 1) {
done(ep0, req, 0);
/* that may have STALLed ep0... */
- UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
- UDC_CTRL_REG = UDC_CLR_EP;
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
- UDC_EP_NUM_REG = UDC_EP_DIR;
+ omap_writew(UDC_EP_SEL | UDC_EP_DIR,
+ UDC_EP_NUM);
+ omap_writew(UDC_CLR_EP, UDC_CTRL);
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+ omap_writew(UDC_EP_DIR, UDC_EP_NUM);
udc->ep0_pending = 0;
}
} else {
/* ack status stage of IN transfer */
- UDC_EP_NUM_REG = 0;
+ omap_writew(0, UDC_EP_NUM);
if (req)
done(ep0, req, 0);
}
} else if (stat & UDC_STALL) {
- UDC_CTRL_REG = UDC_CLR_HALT;
- UDC_EP_NUM_REG = 0;
+ omap_writew(UDC_CLR_HALT, UDC_CTRL);
+ omap_writew(0, UDC_EP_NUM);
} else {
- UDC_EP_NUM_REG = 0;
+ omap_writew(0, UDC_EP_NUM);
}
}
/* read the (latest) SETUP message */
do {
- UDC_EP_NUM_REG = UDC_SETUP_SEL;
+ omap_writew(UDC_SETUP_SEL, UDC_EP_NUM);
/* two bytes at a time */
- u.word[0] = UDC_DATA_REG;
- u.word[1] = UDC_DATA_REG;
- u.word[2] = UDC_DATA_REG;
- u.word[3] = UDC_DATA_REG;
- UDC_EP_NUM_REG = 0;
- } while (UDC_IRQ_SRC_REG & UDC_SETUP);
+ u.word[0] = omap_readw(UDC_DATA);
+ u.word[1] = omap_readw(UDC_DATA);
+ u.word[2] = omap_readw(UDC_DATA);
+ u.word[3] = omap_readw(UDC_DATA);
+ omap_writew(0, UDC_EP_NUM);
+ } while (omap_readw(UDC_IRQ_SRC) & UDC_SETUP);
#define w_value le16_to_cpu(u.r.wValue)
#define w_index le16_to_cpu(u.r.wIndex)
* later if it fails the request.
*/
if (udc->ep0_reset_config)
- UDC_SYSCON2_REG = UDC_CLR_CFG;
+ omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
else
- UDC_SYSCON2_REG = UDC_DEV_CFG;
+ omap_writew(UDC_DEV_CFG, UDC_SYSCON2);
update_otg(udc);
goto delegate;
case USB_REQ_CLEAR_FEATURE:
|| !ep->desc)
goto do_stall;
use_ep(ep, 0);
- UDC_CTRL_REG = udc->clr_halt;
+ omap_writew(udc->clr_halt, UDC_CTRL);
ep->ackwait = 0;
if (!(ep->bEndpointAddress & USB_DIR_IN)) {
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
ep->ackwait = 1 + ep->double_buf;
}
/* NOTE: assumes the host behaves sanely,
}
use_ep(ep, 0);
/* can't halt if fifo isn't empty... */
- UDC_CTRL_REG = UDC_CLR_EP;
- UDC_CTRL_REG = UDC_SET_HALT;
+ omap_writew(UDC_CLR_EP, UDC_CTRL);
+ omap_writew(UDC_SET_HALT, UDC_CTRL);
VDBG("%s halted by host\n", ep->name);
ep0out_status_stage:
status = 0;
- UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
- UDC_CTRL_REG = UDC_CLR_EP;
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
- UDC_EP_NUM_REG = UDC_EP_DIR;
+ omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
+ omap_writew(UDC_CLR_EP, UDC_CTRL);
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+ omap_writew(UDC_EP_DIR, UDC_EP_NUM);
udc->ep0_pending = 0;
break;
case USB_REQ_GET_STATUS:
zero_status:
/* return two zero bytes */
- UDC_EP_NUM_REG = UDC_EP_SEL|UDC_EP_DIR;
- UDC_DATA_REG = 0;
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
- UDC_EP_NUM_REG = UDC_EP_DIR;
+ omap_writew(UDC_EP_SEL|UDC_EP_DIR, UDC_EP_NUM);
+ omap_writew(0, UDC_DATA);
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
+ omap_writew(UDC_EP_DIR, UDC_EP_NUM);
status = 0;
VDBG("GET_STATUS, interface %d\n", w_index);
/* next, status stage */
delegate:
/* activate the ep0out fifo right away */
if (!udc->ep0_in && w_length) {
- UDC_EP_NUM_REG = 0;
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(0, UDC_EP_NUM);
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
}
/* gadget drivers see class/vendor specific requests,
if (udc->ep0_reset_config)
WARN("error resetting config?\n");
else
- UDC_SYSCON2_REG = UDC_CLR_CFG;
+ omap_writew(UDC_CLR_CFG, UDC_SYSCON2);
}
- UDC_SYSCON2_REG = UDC_STALL_CMD;
+ omap_writew(UDC_STALL_CMD, UDC_SYSCON2);
udc->ep0_pending = 0;
}
}
{
u16 devstat, change;
- devstat = UDC_DEVSTAT_REG;
+ devstat = omap_readw(UDC_DEVSTAT);
change = devstat ^ udc->devstat;
udc->devstat = devstat;
INFO("USB reset done, gadget %s\n",
udc->driver->driver.name);
/* ep0 traffic is legal from now on */
- UDC_IRQ_EN_REG = UDC_DS_CHG_IE | UDC_EP0_IE;
+ omap_writew(UDC_DS_CHG_IE | UDC_EP0_IE,
+ UDC_IRQ_EN);
}
change &= ~UDC_USB_RESET;
}
VDBG("devstat %03x, ignore change %03x\n",
devstat, change);
- UDC_IRQ_SRC_REG = UDC_DS_CHG;
+ omap_writew(UDC_DS_CHG, UDC_IRQ_SRC);
}
static irqreturn_t omap_udc_irq(int irq, void *_udc)
unsigned long flags;
spin_lock_irqsave(&udc->lock, flags);
- irq_src = UDC_IRQ_SRC_REG;
+ irq_src = omap_readw(UDC_IRQ_SRC);
/* Device state change (usb ch9 stuff) */
if (irq_src & UDC_DS_CHG) {
irq_src &= ~(UDC_TXN_DONE|UDC_RXN_CNT|UDC_RXN_EOT);
}
- irq_src &= ~(UDC_SOF|UDC_EPN_TX|UDC_EPN_RX);
+ irq_src &= ~(UDC_IRQ_SOF | UDC_EPN_TX|UDC_EPN_RX);
if (irq_src)
DBG("udc_irq, unhandled %03x\n", irq_src);
spin_unlock_irqrestore(&udc->lock, flags);
spin_lock_irqsave(&ep->udc->lock, flags);
if (!list_empty(&ep->queue) && ep->ackwait) {
use_ep(ep, UDC_EP_SEL);
- stat_flg = UDC_STAT_FLG_REG;
+ stat_flg = omap_readw(UDC_STAT_FLG);
if ((stat_flg & UDC_ACK) && (!(stat_flg & UDC_FIFO_EN)
|| (ep->double_buf && HALF_FULL(stat_flg)))) {
req = container_of(ep->queue.next,
struct omap_req, queue);
(void) read_fifo(ep, req);
- UDC_EP_NUM_REG = ep->bEndpointAddress;
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(ep->bEndpointAddress, UDC_EP_NUM);
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
ep->ackwait = 1 + ep->double_buf;
} else
deselect_ep();
unsigned long flags;
spin_lock_irqsave(&udc->lock, flags);
- epn_stat = UDC_EPN_STAT_REG;
- irq_src = UDC_IRQ_SRC_REG;
+ epn_stat = omap_readw(UDC_EPN_STAT);
+ irq_src = omap_readw(UDC_IRQ_SRC);
/* handle OUT first, to avoid some wasteful NAKs */
if (irq_src & UDC_EPN_RX) {
epnum = (epn_stat >> 8) & 0x0f;
- UDC_IRQ_SRC_REG = UDC_EPN_RX;
+ omap_writew(UDC_EPN_RX, UDC_IRQ_SRC);
status = IRQ_HANDLED;
ep = &udc->ep[epnum];
ep->irqs++;
- UDC_EP_NUM_REG = epnum | UDC_EP_SEL;
+ omap_writew(epnum | UDC_EP_SEL, UDC_EP_NUM);
ep->fnf = 0;
- if ((UDC_STAT_FLG_REG & UDC_ACK)) {
+ if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
ep->ackwait--;
if (!list_empty(&ep->queue)) {
int stat;
}
}
/* min 6 clock delay before clearing EP_SEL ... */
- epn_stat = UDC_EPN_STAT_REG;
- epn_stat = UDC_EPN_STAT_REG;
- UDC_EP_NUM_REG = epnum;
+ epn_stat = omap_readw(UDC_EPN_STAT);
+ epn_stat = omap_readw(UDC_EPN_STAT);
+ omap_writew(epnum, UDC_EP_NUM);
/* enabling fifo _after_ clearing ACK, contrary to docs,
* reduces lossage; timer still needed though (sigh).
*/
if (ep->fnf) {
- UDC_CTRL_REG = UDC_SET_FIFO_EN;
+ omap_writew(UDC_SET_FIFO_EN, UDC_CTRL);
ep->ackwait = 1 + ep->double_buf;
}
mod_timer(&ep->timer, PIO_OUT_TIMEOUT);
/* then IN transfers */
else if (irq_src & UDC_EPN_TX) {
epnum = epn_stat & 0x0f;
- UDC_IRQ_SRC_REG = UDC_EPN_TX;
+ omap_writew(UDC_EPN_TX, UDC_IRQ_SRC);
status = IRQ_HANDLED;
ep = &udc->ep[16 + epnum];
ep->irqs++;
- UDC_EP_NUM_REG = epnum | UDC_EP_DIR | UDC_EP_SEL;
- if ((UDC_STAT_FLG_REG & UDC_ACK)) {
+ omap_writew(epnum | UDC_EP_DIR | UDC_EP_SEL, UDC_EP_NUM);
+ if (omap_readw(UDC_STAT_FLG) & UDC_ACK) {
ep->ackwait = 0;
if (!list_empty(&ep->queue)) {
req = container_of(ep->queue.next,
}
}
/* min 6 clock delay before clearing EP_SEL ... */
- epn_stat = UDC_EPN_STAT_REG;
- epn_stat = UDC_EPN_STAT_REG;
- UDC_EP_NUM_REG = epnum | UDC_EP_DIR;
+ epn_stat = omap_readw(UDC_EPN_STAT);
+ epn_stat = omap_readw(UDC_EPN_STAT);
+ omap_writew(epnum | UDC_EP_DIR, UDC_EP_NUM);
/* then 6 clocks before it'd tx */
}
req = list_entry(ep->queue.next, struct omap_req, queue);
use_ep(ep, UDC_EP_SEL);
- stat = UDC_STAT_FLG_REG;
+ stat = omap_readw(UDC_STAT_FLG);
/* NOTE: like the other controller drivers, this isn't
* currently reporting lost or damaged frames.
if (!list_empty(&ep->queue))
pending = 1;
}
- if (!pending)
- UDC_IRQ_EN_REG &= ~UDC_SOF_IE;
- UDC_IRQ_SRC_REG = UDC_SOF;
+ if (!pending) {
+ u16 w;
+
+ w = omap_readw(UDC_IRQ_EN);
+ w &= ~UDC_SOF_IE;
+ omap_writew(w, UDC_IRQ_EN);
+ }
+ omap_writew(UDC_IRQ_SOF, UDC_IRQ_SRC);
spin_unlock_irqrestore(&udc->lock, flags);
return IRQ_HANDLED;
if (ep->bmAttributes == USB_ENDPOINT_XFER_ISOC)
continue;
use_ep(ep, 0);
- UDC_CTRL_REG = UDC_SET_HALT;
+ omap_writew(UDC_SET_HALT, UDC_CTRL);
}
udc->ep0_pending = 0;
udc->ep[0].irqs = 0;
}
DBG("bound to driver %s\n", driver->driver.name);
- UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
+ omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
/* connect to bus through transceiver */
if (udc->transceiver) {
else
buf[0] = 0;
- stat_flg = UDC_STAT_FLG_REG;
+ stat_flg = omap_readw(UDC_STAT_FLG);
seq_printf(s,
"\n%s %s%s%sirqs %ld stat %04x " EIGHTBITS FOURBITS "%s\n",
ep->name, buf,
trans = CONTROL_DEVCONF_REG;
} else {
ctrl_name = "tranceiver_ctrl";
- trans = USB_TRANSCEIVER_CTRL_REG;
+ trans = omap_readw(USB_TRANSCEIVER_CTRL);
}
seq_printf(s, "\nOTG rev %d.%d, %s %05x\n",
tmp >> 4, tmp & 0xf, ctrl_name, trans);
- tmp = OTG_SYSCON_1_REG;
+ tmp = omap_readw(OTG_SYSCON_1);
seq_printf(s, "otg_syscon1 %08x usb2 %s, usb1 %s, usb0 %s,"
FOURBITS "\n", tmp,
trx_mode(USB2_TRX_MODE(tmp), trans & CONF_USB2_UNI_R),
(tmp & HST_IDLE_EN) ? " !host" : "",
(tmp & DEV_IDLE_EN) ? " !dev" : "",
(tmp & OTG_RESET_DONE) ? " reset_done" : " reset_active");
- tmp = OTG_SYSCON_2_REG;
+ tmp = omap_readl(OTG_SYSCON_2);
seq_printf(s, "otg_syscon2 %08x%s" EIGHTBITS
" b_ase_brst=%d hmc=%d\n", tmp,
(tmp & OTG_EN) ? " otg_en" : "",
(tmp & HMC_TLLATTACH) ? " tllattach" : "",
B_ASE_BRST(tmp),
OTG_HMC(tmp));
- tmp = OTG_CTRL_REG;
+ tmp = omap_readl(OTG_CTRL);
seq_printf(s, "otg_ctrl %06x" EIGHTBITS EIGHTBITS "%s\n", tmp,
(tmp & OTG_ASESSVLD) ? " asess" : "",
(tmp & OTG_BSESSEND) ? " bsess_end" : "",
(tmp & OTG_PU_VBUS) ? " pu_vb" : "",
(tmp & OTG_PU_ID) ? " pu_id" : ""
);
- tmp = OTG_IRQ_EN_REG;
+ tmp = omap_readw(OTG_IRQ_EN);
seq_printf(s, "otg_irq_en %04x" "\n", tmp);
- tmp = OTG_IRQ_SRC_REG;
+ tmp = omap_readw(OTG_IRQ_SRC);
seq_printf(s, "otg_irq_src %04x" "\n", tmp);
- tmp = OTG_OUTCTRL_REG;
+ tmp = omap_readw(OTG_OUTCTRL);
seq_printf(s, "otg_outctrl %04x" "\n", tmp);
- tmp = OTG_TEST_REG;
+ tmp = omap_readw(OTG_TEST);
seq_printf(s, "otg_test %04x" "\n", tmp);
return 0;
}
driver_desc,
use_dma ? " (dma)" : "");
- tmp = UDC_REV_REG & 0xff;
+ tmp = omap_readw(UDC_REV) & 0xff;
seq_printf(s,
"UDC rev %d.%d, fifo mode %d, gadget %s\n"
"hmc %d, transceiver %s\n",
? "external" : "(none)"));
if (cpu_class_is_omap1()) {
seq_printf(s, "ULPD control %04x req %04x status %04x\n",
- __REG16(ULPD_CLOCK_CTRL),
- __REG16(ULPD_SOFT_REQ),
- __REG16(ULPD_STATUS_REQ));
+ omap_readw(ULPD_CLOCK_CTRL),
+ omap_readw(ULPD_SOFT_REQ),
+ omap_readw(ULPD_STATUS_REQ));
}
/* OTG controller registers */
if (!cpu_is_omap15xx())
proc_otg_show(s);
- tmp = UDC_SYSCON1_REG;
+ tmp = omap_readw(UDC_SYSCON1);
seq_printf(s, "\nsyscon1 %04x" EIGHTBITS "\n", tmp,
(tmp & UDC_CFG_LOCK) ? " cfg_lock" : "",
(tmp & UDC_DATA_ENDIAN) ? " data_endian" : "",
return 0;
}
- tmp = UDC_DEVSTAT_REG;
+ tmp = omap_readw(UDC_DEVSTAT);
seq_printf(s, "devstat %04x" EIGHTBITS "%s%s\n", tmp,
(tmp & UDC_B_HNP_ENABLE) ? " b_hnp" : "",
(tmp & UDC_A_HNP_SUPPORT) ? " a_hnp" : "",
(tmp & UDC_ADD) ? " ADD" : "",
(tmp & UDC_DEF) ? " DEF" : "",
(tmp & UDC_ATT) ? " ATT" : "");
- seq_printf(s, "sof %04x\n", UDC_SOF_REG);
- tmp = UDC_IRQ_EN_REG;
+ seq_printf(s, "sof %04x\n", omap_readw(UDC_SOF));
+ tmp = omap_readw(UDC_IRQ_EN);
seq_printf(s, "irq_en %04x" FOURBITS "%s\n", tmp,
(tmp & UDC_SOF_IE) ? " sof" : "",
(tmp & UDC_EPN_RX_IE) ? " epn_rx" : "",
(tmp & UDC_EPN_TX_IE) ? " epn_tx" : "",
(tmp & UDC_DS_CHG_IE) ? " ds_chg" : "",
(tmp & UDC_EP0_IE) ? " ep0" : "");
- tmp = UDC_IRQ_SRC_REG;
+ tmp = omap_readw(UDC_IRQ_SRC);
seq_printf(s, "irq_src %04x" EIGHTBITS "%s%s\n", tmp,
(tmp & UDC_TXN_DONE) ? " txn_done" : "",
(tmp & UDC_RXN_CNT) ? " rxn_cnt" : "",
(tmp & UDC_RXN_EOT) ? " rxn_eot" : "",
- (tmp & UDC_SOF) ? " sof" : "",
+ (tmp & UDC_IRQ_SOF) ? " sof" : "",
(tmp & UDC_EPN_RX) ? " epn_rx" : "",
(tmp & UDC_EPN_TX) ? " epn_tx" : "",
(tmp & UDC_DS_CHG) ? " ds_chg" : "",
if (use_dma) {
unsigned i;
- tmp = UDC_DMA_IRQ_EN_REG;
+ tmp = omap_readw(UDC_DMA_IRQ_EN);
seq_printf(s, "dma_irq_en %04x%s" EIGHTBITS "\n", tmp,
(tmp & UDC_TX_DONE_IE(3)) ? " tx2_done" : "",
(tmp & UDC_RX_CNT_IE(3)) ? " rx2_cnt" : "",
(tmp & UDC_RX_CNT_IE(1)) ? " rx0_cnt" : "",
(tmp & UDC_RX_EOT_IE(1)) ? " rx0_eot" : "");
- tmp = UDC_RXDMA_CFG_REG;
+ tmp = omap_readw(UDC_RXDMA_CFG);
seq_printf(s, "rxdma_cfg %04x\n", tmp);
if (tmp) {
for (i = 0; i < 3; i++) {
if ((tmp & (0x0f << (i * 4))) == 0)
continue;
seq_printf(s, "rxdma[%d] %04x\n", i,
- UDC_RXDMA_REG(i + 1));
+ omap_readw(UDC_RXDMA(i + 1)));
}
}
- tmp = UDC_TXDMA_CFG_REG;
+ tmp = omap_readw(UDC_TXDMA_CFG);
seq_printf(s, "txdma_cfg %04x\n", tmp);
if (tmp) {
for (i = 0; i < 3; i++) {
if (!(tmp & (0x0f << (i * 4))))
continue;
seq_printf(s, "txdma[%d] %04x\n", i,
- UDC_TXDMA_REG(i + 1));
+ omap_readw(UDC_TXDMA(i + 1)));
}
}
}
- tmp = UDC_DEVSTAT_REG;
+ tmp = omap_readw(UDC_DEVSTAT);
if (tmp & UDC_ATT) {
proc_ep_show(s, &udc->ep[0]);
if (tmp & UDC_ADD) {
* buffer space among the endpoints we'll be operating.
*
* NOTE: as of OMAP 1710 ES2.0, writing a new endpoint config when
- * UDC_SYSCON_1_REG.CFG_LOCK is set can now work. We won't use that
+ * UDC_SYSCON_1.CFG_LOCK is set can now work. We won't use that
* capability yet though.
*/
static unsigned __init
name, addr, epn_rxtx, maxp, dbuf ? "x2" : "", buf);
if (addr & USB_DIR_IN)
- UDC_EP_TX_REG(addr & 0xf) = epn_rxtx;
+ omap_writew(epn_rxtx, UDC_EP_TX(addr & 0xf));
else
- UDC_EP_RX_REG(addr) = epn_rxtx;
+ omap_writew(epn_rxtx, UDC_EP_RX(addr));
/* next endpoint's buffer starts after this one's */
buf += maxp;
unsigned tmp, buf;
/* abolish any previous hardware state */
- UDC_SYSCON1_REG = 0;
- UDC_IRQ_EN_REG = 0;
- UDC_IRQ_SRC_REG = UDC_IRQ_SRC_MASK;
- UDC_DMA_IRQ_EN_REG = 0;
- UDC_RXDMA_CFG_REG = 0;
- UDC_TXDMA_CFG_REG = 0;
+ omap_writew(0, UDC_SYSCON1);
+ omap_writew(0, UDC_IRQ_EN);
+ omap_writew(UDC_IRQ_SRC_MASK, UDC_IRQ_SRC);
+ omap_writew(0, UDC_DMA_IRQ_EN);
+ omap_writew(0, UDC_RXDMA_CFG);
+ omap_writew(0, UDC_TXDMA_CFG);
/* UDC_PULLUP_EN gates the chip clock */
- // OTG_SYSCON_1_REG |= DEV_IDLE_EN;
+ // OTG_SYSCON_1 |= DEV_IDLE_EN;
udc = kzalloc(sizeof(*udc), GFP_KERNEL);
if (!udc)
/* initially disable all non-ep0 endpoints */
for (tmp = 1; tmp < 15; tmp++) {
- UDC_EP_RX_REG(tmp) = 0;
- UDC_EP_TX_REG(tmp) = 0;
+ omap_writew(0, UDC_EP_RX(tmp));
+ omap_writew(0, UDC_EP_TX(tmp));
}
#define OMAP_BULK_EP(name,addr) \
ERR("unsupported fifo_mode #%d\n", fifo_mode);
return -ENODEV;
}
- UDC_SYSCON1_REG = UDC_CFG_LOCK|UDC_SELF_PWR;
+ omap_writew(UDC_CFG_LOCK|UDC_SELF_PWR, UDC_SYSCON1);
INFO("fifo mode %d, %d bytes not used\n", fifo_mode, 2048 - buf);
return 0;
}
}
INFO("OMAP UDC rev %d.%d%s\n",
- UDC_REV_REG >> 4, UDC_REV_REG & 0xf,
+ omap_readw(UDC_REV) >> 4, omap_readw(UDC_REV) & 0xf,
config->otg ? ", Mini-AB" : "");
/* use the mode given to us by board init code */
* know when to turn PULLUP_EN on/off; and that
* means we always "need" the 48MHz clock.
*/
- u32 tmp = FUNC_MUX_CTRL_0_REG;
-
- FUNC_MUX_CTRL_0_REG &= ~VBUS_CTRL_1510;
+ u32 tmp = omap_readl(FUNC_MUX_CTRL_0);
+ tmp &= ~VBUS_CTRL_1510;
+ omap_writel(tmp, FUNC_MUX_CTRL_0);
tmp |= VBUS_MODE_1510;
tmp &= ~VBUS_CTRL_1510;
- FUNC_MUX_CTRL_0_REG = tmp;
+ omap_writel(tmp, FUNC_MUX_CTRL_0);
}
} else {
/* The transceiver may package some GPIO logic or handle
#endif
/* starting with omap1710 es2.0, clear toggle is a separate bit */
- if (UDC_REV_REG >= 0x61)
+ if (omap_readw(UDC_REV) >= 0x61)
udc->clr_halt = UDC_RESET_EP | UDC_CLRDATA_TOGGLE;
else
udc->clr_halt = UDC_RESET_EP;
put_device(udc->transceiver->dev);
udc->transceiver = NULL;
}
- UDC_SYSCON1_REG = 0;
+ omap_writew(0, UDC_SYSCON1);
remove_proc_file();
*
* REVISIT we should probably reject suspend requests when there's a host
* session active, rather than disconnecting, at least on boards that can
- * report VBUS irqs (UDC_DEVSTAT_REG.UDC_ATT). And in any case, we need to
+ * report VBUS irqs (UDC_DEVSTAT.UDC_ATT). And in any case, we need to
* make host resumes and VBUS detection trigger OMAP wakeup events; that
* may involve talking to an external transceiver (e.g. isp1301).
*/
{
u32 devstat;
- devstat = UDC_DEVSTAT_REG;
+ devstat = omap_readw(UDC_DEVSTAT);
/* we're requesting 48 MHz clock if the pullup is enabled
* (== we're attached to the host) and we're not suspended,
projects / linux-2.6-omap-h63xx.git / blobdiff