/*******************************************************************
* This file is part of the Emulex Linux Device Driver for *
* Fibre Channel Host Bus Adapters. *
- * Copyright (C) 2004-2005 Emulex. All rights reserved. *
+ * Copyright (C) 2004-2006 Emulex. All rights reserved. *
* EMULEX and SLI are trademarks of Emulex. *
* www.emulex.com *
* Portions Copyright (C) 2004-2005 Christoph Hellwig *
LPFC_ABORT_IOCB
} lpfc_iocb_type;
+struct lpfc_iocbq *
+lpfc_sli_get_iocbq(struct lpfc_hba * phba)
+{
+ struct list_head *lpfc_iocb_list = &phba->lpfc_iocb_list;
+ struct lpfc_iocbq * iocbq = NULL;
+
+ list_remove_head(lpfc_iocb_list, iocbq, struct lpfc_iocbq, list);
+ return iocbq;
+}
+
void
lpfc_sli_release_iocbq(struct lpfc_hba * phba, struct lpfc_iocbq * iocbq)
{
case MBX_SET_MASK:
case MBX_SET_SLIM:
case MBX_UNREG_D_ID:
+ case MBX_KILL_BOARD:
case MBX_CONFIG_FARP:
+ case MBX_BEACON:
case MBX_LOAD_AREA:
case MBX_RUN_BIU_DIAG64:
case MBX_CONFIG_PORT:
}
/* unSolicited Responses */
if (pring->prt[0].profile) {
- (pring->prt[0].lpfc_sli_rcv_unsol_event) (phba, pring, saveq);
+ if (pring->prt[0].lpfc_sli_rcv_unsol_event)
+ (pring->prt[0].lpfc_sli_rcv_unsol_event) (phba, pring,
+ saveq);
match = 1;
} else {
/* We must search, based on rctl / type
Rctl)
&& (pring->prt[i].
type == Type)) {
- (pring->prt[i].lpfc_sli_rcv_unsol_event)
- (phba, pring, saveq);
+ if (pring->prt[i].lpfc_sli_rcv_unsol_event)
+ (pring->prt[i].lpfc_sli_rcv_unsol_event)
+ (phba, pring, saveq);
match = 1;
break;
}
spin_lock_irqsave(phba->host->host_lock, iflag);
}
else {
- if (cmdiocbp->iocb_flag & LPFC_IO_POLL)
- rc = 0;
-
spin_unlock_irqrestore(phba->host->host_lock,
iflag);
(cmdiocbp->iocb_cmpl) (phba, cmdiocbp, saveq);
saveq->iocb.ulpContext);
}
}
+
spin_unlock_irqrestore(phba->host->host_lock, iflag);
return rc;
}
+static void lpfc_sli_rsp_pointers_error(struct lpfc_hba * phba,
+ struct lpfc_sli_ring * pring)
+{
+ struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
+ /*
+ * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
+ * rsp ring <portRspMax>
+ */
+ lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
+ "%d:0312 Ring %d handler: portRspPut %d "
+ "is bigger then rsp ring %d\n",
+ phba->brd_no, pring->ringno,
+ le32_to_cpu(pgp->rspPutInx),
+ pring->numRiocb);
+
+ phba->hba_state = LPFC_HBA_ERROR;
+
+ /*
+ * All error attention handlers are posted to
+ * worker thread
+ */
+ phba->work_ha |= HA_ERATT;
+ phba->work_hs = HS_FFER3;
+ if (phba->work_wait)
+ wake_up(phba->work_wait);
+
+ return;
+}
+
+void lpfc_sli_poll_fcp_ring(struct lpfc_hba * phba)
+{
+ struct lpfc_sli * psli = &phba->sli;
+ struct lpfc_sli_ring * pring = &psli->ring[LPFC_FCP_RING];
+ IOCB_t *irsp = NULL;
+ IOCB_t *entry = NULL;
+ struct lpfc_iocbq *cmdiocbq = NULL;
+ struct lpfc_iocbq rspiocbq;
+ struct lpfc_pgp *pgp;
+ uint32_t status;
+ uint32_t portRspPut, portRspMax;
+ int type;
+ uint32_t rsp_cmpl = 0;
+ void __iomem *to_slim;
+ uint32_t ha_copy;
+
+ pring->stats.iocb_event++;
+
+ /* The driver assumes SLI-2 mode */
+ pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
+
+ /*
+ * The next available response entry should never exceed the maximum
+ * entries. If it does, treat it as an adapter hardware error.
+ */
+ portRspMax = pring->numRiocb;
+ portRspPut = le32_to_cpu(pgp->rspPutInx);
+ if (unlikely(portRspPut >= portRspMax)) {
+ lpfc_sli_rsp_pointers_error(phba, pring);
+ return;
+ }
+
+ rmb();
+ while (pring->rspidx != portRspPut) {
+
+ entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
+
+ if (++pring->rspidx >= portRspMax)
+ pring->rspidx = 0;
+
+ lpfc_sli_pcimem_bcopy((uint32_t *) entry,
+ (uint32_t *) &rspiocbq.iocb,
+ sizeof (IOCB_t));
+ irsp = &rspiocbq.iocb;
+ type = lpfc_sli_iocb_cmd_type(irsp->ulpCommand & CMD_IOCB_MASK);
+ pring->stats.iocb_rsp++;
+ rsp_cmpl++;
+
+ if (unlikely(irsp->ulpStatus)) {
+ /* Rsp ring <ringno> error: IOCB */
+ lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
+ "%d:0326 Rsp Ring %d error: IOCB Data: "
+ "x%x x%x x%x x%x x%x x%x x%x x%x\n",
+ phba->brd_no, pring->ringno,
+ irsp->un.ulpWord[0],
+ irsp->un.ulpWord[1],
+ irsp->un.ulpWord[2],
+ irsp->un.ulpWord[3],
+ irsp->un.ulpWord[4],
+ irsp->un.ulpWord[5],
+ *(((uint32_t *) irsp) + 6),
+ *(((uint32_t *) irsp) + 7));
+ }
+
+ switch (type) {
+ case LPFC_ABORT_IOCB:
+ case LPFC_SOL_IOCB:
+ /*
+ * Idle exchange closed via ABTS from port. No iocb
+ * resources need to be recovered.
+ */
+ if (unlikely(irsp->ulpCommand == CMD_XRI_ABORTED_CX)) {
+ printk(KERN_INFO "%s: IOCB cmd 0x%x processed."
+ " Skipping completion\n", __FUNCTION__,
+ irsp->ulpCommand);
+ break;
+ }
+
+ cmdiocbq = lpfc_sli_iocbq_lookup(phba, pring,
+ &rspiocbq);
+ if ((cmdiocbq) && (cmdiocbq->iocb_cmpl)) {
+ (cmdiocbq->iocb_cmpl)(phba, cmdiocbq,
+ &rspiocbq);
+ }
+ break;
+ default:
+ if (irsp->ulpCommand == CMD_ADAPTER_MSG) {
+ char adaptermsg[LPFC_MAX_ADPTMSG];
+ memset(adaptermsg, 0, LPFC_MAX_ADPTMSG);
+ memcpy(&adaptermsg[0], (uint8_t *) irsp,
+ MAX_MSG_DATA);
+ dev_warn(&((phba->pcidev)->dev), "lpfc%d: %s",
+ phba->brd_no, adaptermsg);
+ } else {
+ /* Unknown IOCB command */
+ lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
+ "%d:0321 Unknown IOCB command "
+ "Data: x%x, x%x x%x x%x x%x\n",
+ phba->brd_no, type,
+ irsp->ulpCommand,
+ irsp->ulpStatus,
+ irsp->ulpIoTag,
+ irsp->ulpContext);
+ }
+ break;
+ }
+
+ /*
+ * The response IOCB has been processed. Update the ring
+ * pointer in SLIM. If the port response put pointer has not
+ * been updated, sync the pgp->rspPutInx and fetch the new port
+ * response put pointer.
+ */
+ to_slim = phba->MBslimaddr +
+ (SLIMOFF + (pring->ringno * 2) + 1) * 4;
+ writeb(pring->rspidx, to_slim);
+
+ if (pring->rspidx == portRspPut)
+ portRspPut = le32_to_cpu(pgp->rspPutInx);
+ }
+
+ ha_copy = readl(phba->HAregaddr);
+ ha_copy >>= (LPFC_FCP_RING * 4);
+
+ if ((rsp_cmpl > 0) && (ha_copy & HA_R0RE_REQ)) {
+ pring->stats.iocb_rsp_full++;
+ status = ((CA_R0ATT | CA_R0RE_RSP) << (LPFC_FCP_RING * 4));
+ writel(status, phba->CAregaddr);
+ readl(phba->CAregaddr);
+ }
+ if ((ha_copy & HA_R0CE_RSP) &&
+ (pring->flag & LPFC_CALL_RING_AVAILABLE)) {
+ pring->flag &= ~LPFC_CALL_RING_AVAILABLE;
+ pring->stats.iocb_cmd_empty++;
+
+ /* Force update of the local copy of cmdGetInx */
+ pring->local_getidx = le32_to_cpu(pgp->cmdGetInx);
+ lpfc_sli_resume_iocb(phba, pring);
+
+ if ((pring->lpfc_sli_cmd_available))
+ (pring->lpfc_sli_cmd_available) (phba, pring);
+
+ }
+
+ return;
+}
+
/*
* This routine presumes LPFC_FCP_RING handling and doesn't bother
* to check it explicitly.
portRspMax = pring->numRiocb;
portRspPut = le32_to_cpu(pgp->rspPutInx);
if (unlikely(portRspPut >= portRspMax)) {
- /*
- * Ring <ringno> handler: portRspPut <portRspPut> is bigger then
- * rsp ring <portRspMax>
- */
- lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
- "%d:0312 Ring %d handler: portRspPut %d "
- "is bigger then rsp ring %d\n",
- phba->brd_no, pring->ringno, portRspPut,
- portRspMax);
-
- phba->hba_state = LPFC_HBA_ERROR;
-
- /* All error attention handlers are posted to worker thread */
- phba->work_ha |= HA_ERATT;
- phba->work_hs = HS_FFER3;
- if (phba->work_wait)
- wake_up(phba->work_wait);
-
+ lpfc_sli_rsp_pointers_error(phba, pring);
spin_unlock_irqrestore(phba->host->host_lock, iflag);
return 1;
}
* structure. The copy involves a byte-swap since the
* network byte order and pci byte orders are different.
*/
- entry = (IOCB_t *) IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
+ entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
+
+ if (++pring->rspidx >= portRspMax)
+ pring->rspidx = 0;
+
lpfc_sli_pcimem_bcopy((uint32_t *) entry,
(uint32_t *) &rspiocbq.iocb,
sizeof (IOCB_t));
* been updated, sync the pgp->rspPutInx and fetch the new port
* response put pointer.
*/
- if (++pring->rspidx >= portRspMax)
- pring->rspidx = 0;
-
to_slim = phba->MBslimaddr +
(SLIMOFF + (pring->ringno * 2) + 1) * 4;
writel(pring->rspidx, to_slim);
struct lpfc_iocbq *next_iocb;
struct lpfc_iocbq *cmdiocbp;
struct lpfc_iocbq *saveq;
- struct list_head *lpfc_iocb_list = &phba->lpfc_iocb_list;
struct lpfc_pgp *pgp = &phba->slim2p->mbx.us.s2.port[pring->ringno];
uint8_t iocb_cmd_type;
lpfc_iocb_type type;
}
rmb();
- lpfc_iocb_list = &phba->lpfc_iocb_list;
while (pring->rspidx != portRspPut) {
/*
* Build a completion list and call the appropriate handler.
* received.
*/
entry = IOCB_ENTRY(pring->rspringaddr, pring->rspidx);
- list_remove_head(lpfc_iocb_list, rspiocbp, struct lpfc_iocbq,
- list);
+ rspiocbp = lpfc_sli_get_iocbq(phba);
if (rspiocbp == NULL) {
printk(KERN_ERR "%s: out of buffers! Failing "
"completion.\n", __FUNCTION__);
return errcnt;
}
-/******************************************************************************
-* lpfc_sli_send_reset
-*
-* Note: After returning from this function, the HBA cannot be accessed for
-* 1 ms. Since we do not wish to delay in interrupt context, it is the
-* responsibility of the caller to perform the mdelay(1) and flush via readl().
-******************************************************************************/
-static int
-lpfc_sli_send_reset(struct lpfc_hba * phba, uint16_t skip_post)
+int
+lpfc_sli_brdready(struct lpfc_hba * phba, uint32_t mask)
{
- MAILBOX_t *swpmb;
- volatile uint32_t word0;
- void __iomem *to_slim;
- unsigned long flags = 0;
+ uint32_t status;
+ int i = 0;
+ int retval = 0;
- spin_lock_irqsave(phba->host->host_lock, flags);
+ /* Read the HBA Host Status Register */
+ status = readl(phba->HSregaddr);
- /* A board reset must use REAL SLIM. */
- phba->sli.sli_flag &= ~LPFC_SLI2_ACTIVE;
+ /*
+ * Check status register every 100ms for 5 retries, then every
+ * 500ms for 5, then every 2.5 sec for 5, then reset board and
+ * every 2.5 sec for 4.
+ * Break our of the loop if errors occurred during init.
+ */
+ while (((status & mask) != mask) &&
+ !(status & HS_FFERM) &&
+ i++ < 20) {
- word0 = 0;
- swpmb = (MAILBOX_t *) & word0;
- swpmb->mbxCommand = MBX_RESTART;
- swpmb->mbxHc = 1;
+ if (i <= 5)
+ msleep(10);
+ else if (i <= 10)
+ msleep(500);
+ else
+ msleep(2500);
- to_slim = phba->MBslimaddr;
- writel(*(uint32_t *) swpmb, to_slim);
- readl(to_slim); /* flush */
+ if (i == 15) {
+ phba->hba_state = LPFC_STATE_UNKNOWN; /* Do post */
+ lpfc_sli_brdrestart(phba);
+ }
+ /* Read the HBA Host Status Register */
+ status = readl(phba->HSregaddr);
+ }
- /* Only skip post after fc_ffinit is completed */
- if (skip_post) {
- word0 = 1; /* This is really setting up word1 */
- } else {
- word0 = 0; /* This is really setting up word1 */
+ /* Check to see if any errors occurred during init */
+ if ((status & HS_FFERM) || (i >= 20)) {
+ phba->hba_state = LPFC_HBA_ERROR;
+ retval = 1;
}
- to_slim = phba->MBslimaddr + sizeof (uint32_t);
- writel(*(uint32_t *) swpmb, to_slim);
- readl(to_slim); /* flush */
- /* Turn off parity checking and serr during the physical reset */
- pci_read_config_word(phba->pcidev, PCI_COMMAND, &phba->pci_cfg_value);
- pci_write_config_word(phba->pcidev, PCI_COMMAND,
- (phba->pci_cfg_value &
- ~(PCI_COMMAND_PARITY | PCI_COMMAND_SERR)));
+ return retval;
+}
- writel(HC_INITFF, phba->HCregaddr);
+int
+lpfc_sli_brdkill(struct lpfc_hba * phba)
+{
+ struct lpfc_sli *psli;
+ LPFC_MBOXQ_t *pmb;
+ uint32_t status;
+ uint32_t ha_copy;
+ int retval;
+ int i = 0;
- phba->hba_state = LPFC_INIT_START;
- spin_unlock_irqrestore(phba->host->host_lock, flags);
+ psli = &phba->sli;
- return 0;
+ /* Kill HBA */
+ lpfc_printf_log(phba,
+ KERN_INFO,
+ LOG_SLI,
+ "%d:0329 Kill HBA Data: x%x x%x\n",
+ phba->brd_no,
+ phba->hba_state,
+ psli->sli_flag);
+
+ if ((pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
+ GFP_ATOMIC)) == 0) {
+ return 1;
+ }
+
+ /* Disable the error attention */
+ spin_lock_irq(phba->host->host_lock);
+ status = readl(phba->HCregaddr);
+ status &= ~HC_ERINT_ENA;
+ writel(status, phba->HCregaddr);
+ readl(phba->HCregaddr); /* flush */
+ spin_unlock_irq(phba->host->host_lock);
+
+ lpfc_kill_board(phba, pmb);
+ pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
+ retval = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
+
+ if (retval != MBX_SUCCESS) {
+ if (retval != MBX_BUSY)
+ mempool_free(pmb, phba->mbox_mem_pool);
+ return 1;
+ }
+
+ mempool_free(pmb, phba->mbox_mem_pool);
+
+ /* There is no completion for a KILL_BOARD mbox cmd. Check for an error
+ * attention every 100ms for 3 seconds. If we don't get ERATT after
+ * 3 seconds we still set HBA_ERROR state because the status of the
+ * board is now undefined.
+ */
+ ha_copy = readl(phba->HAregaddr);
+
+ while ((i++ < 30) && !(ha_copy & HA_ERATT)) {
+ mdelay(100);
+ ha_copy = readl(phba->HAregaddr);
+ }
+
+ del_timer_sync(&psli->mbox_tmo);
+
+ spin_lock_irq(phba->host->host_lock);
+ psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
+ spin_unlock_irq(phba->host->host_lock);
+
+ psli->mbox_active = NULL;
+ lpfc_hba_down_post(phba);
+ phba->hba_state = LPFC_HBA_ERROR;
+
+ return (ha_copy & HA_ERATT ? 0 : 1);
}
-static int
-lpfc_sli_brdreset(struct lpfc_hba * phba, uint16_t skip_post)
+int
+lpfc_sli_brdreset(struct lpfc_hba * phba)
{
+ struct lpfc_sli *psli;
struct lpfc_sli_ring *pring;
+ uint16_t cfg_value;
int i;
- struct lpfc_dmabuf *mp, *next_mp;
- unsigned long flags = 0;
-
- lpfc_sli_send_reset(phba, skip_post);
- mdelay(1);
- spin_lock_irqsave(phba->host->host_lock, flags);
- /* Risk the write on flush case ie no delay after the readl */
- readl(phba->HCregaddr); /* flush */
- /* Now toggle INITFF bit set by lpfc_sli_send_reset */
- writel(0, phba->HCregaddr);
- readl(phba->HCregaddr); /* flush */
+ psli = &phba->sli;
- /* Restore PCI cmd register */
- pci_write_config_word(phba->pcidev, PCI_COMMAND, phba->pci_cfg_value);
+ /* Reset HBA */
+ lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
+ "%d:0325 Reset HBA Data: x%x x%x\n", phba->brd_no,
+ phba->hba_state, psli->sli_flag);
/* perform board reset */
phba->fc_eventTag = 0;
phba->fc_myDID = 0;
- phba->fc_prevDID = Mask_DID;
+ phba->fc_prevDID = 0;
- /* Reset HBA */
- lpfc_printf_log(phba,
- KERN_INFO,
- LOG_SLI,
- "%d:0325 Reset HBA Data: x%x x%x x%x\n",
- phba->brd_no,
- phba->hba_state,
- phba->sli.sli_flag,
- skip_post);
+ psli->sli_flag = 0;
+
+ /* Turn off parity checking and serr during the physical reset */
+ pci_read_config_word(phba->pcidev, PCI_COMMAND, &cfg_value);
+ pci_write_config_word(phba->pcidev, PCI_COMMAND,
+ (cfg_value &
+ ~(PCI_COMMAND_PARITY | PCI_COMMAND_SERR)));
+
+ /* Now toggle INITFF bit in the Host Control Register */
+ writel(HC_INITFF, phba->HCregaddr);
+ mdelay(1);
+ readl(phba->HCregaddr); /* flush */
+ writel(0, phba->HCregaddr);
+ readl(phba->HCregaddr); /* flush */
+
+ /* Restore PCI cmd register */
+ pci_write_config_word(phba->pcidev, PCI_COMMAND, cfg_value);
/* Initialize relevant SLI info */
- for (i = 0; i < phba->sli.num_rings; i++) {
- pring = &phba->sli.ring[i];
+ for (i = 0; i < psli->num_rings; i++) {
+ pring = &psli->ring[i];
pring->flag = 0;
pring->rspidx = 0;
pring->next_cmdidx = 0;
pring->cmdidx = 0;
pring->missbufcnt = 0;
}
- spin_unlock_irqrestore(phba->host->host_lock, flags);
- if (skip_post) {
- mdelay(100);
+ phba->hba_state = LPFC_WARM_START;
+ return 0;
+}
+
+int
+lpfc_sli_brdrestart(struct lpfc_hba * phba)
+{
+ MAILBOX_t *mb;
+ struct lpfc_sli *psli;
+ uint16_t skip_post;
+ volatile uint32_t word0;
+ void __iomem *to_slim;
+
+ spin_lock_irq(phba->host->host_lock);
+
+ psli = &phba->sli;
+
+ /* Restart HBA */
+ lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
+ "%d:0328 Restart HBA Data: x%x x%x\n", phba->brd_no,
+ phba->hba_state, psli->sli_flag);
+
+ word0 = 0;
+ mb = (MAILBOX_t *) &word0;
+ mb->mbxCommand = MBX_RESTART;
+ mb->mbxHc = 1;
+
+ to_slim = phba->MBslimaddr;
+ writel(*(uint32_t *) mb, to_slim);
+ readl(to_slim); /* flush */
+
+ /* Only skip post after fc_ffinit is completed */
+ if (phba->hba_state) {
+ skip_post = 1;
+ word0 = 1; /* This is really setting up word1 */
} else {
- mdelay(2000);
+ skip_post = 0;
+ word0 = 0; /* This is really setting up word1 */
}
+ to_slim = (uint8_t *) phba->MBslimaddr + sizeof (uint32_t);
+ writel(*(uint32_t *) mb, to_slim);
+ readl(to_slim); /* flush */
- spin_lock_irqsave(phba->host->host_lock, flags);
- /* Cleanup preposted buffers on the ELS ring */
- pring = &phba->sli.ring[LPFC_ELS_RING];
- list_for_each_entry_safe(mp, next_mp, &pring->postbufq, list) {
- list_del(&mp->list);
- pring->postbufq_cnt--;
- lpfc_mbuf_free(phba, mp->virt, mp->phys);
- kfree(mp);
- }
- spin_unlock_irqrestore(phba->host->host_lock, flags);
+ lpfc_sli_brdreset(phba);
- for (i = 0; i < phba->sli.num_rings; i++)
- lpfc_sli_abort_iocb_ring(phba, &phba->sli.ring[i]);
+ phba->hba_state = LPFC_INIT_START;
+
+ spin_unlock_irq(phba->host->host_lock);
+
+ if (skip_post)
+ mdelay(100);
+ else
+ mdelay(2000);
+
+ lpfc_hba_down_post(phba);
return 0;
}
}
if (i == 15) {
- lpfc_sli_brdreset(phba, 0);
+ phba->hba_state = LPFC_STATE_UNKNOWN; /* Do post */
+ lpfc_sli_brdrestart(phba);
}
/* Read the HBA Host Status Register */
status = readl(phba->HSregaddr);
}
while (resetcount < 2 && !done) {
- phba->hba_state = 0;
- lpfc_sli_brdreset(phba, 0);
+ phba->hba_state = LPFC_STATE_UNKNOWN;
+ lpfc_sli_brdrestart(phba);
msleep(2500);
rc = lpfc_sli_chipset_init(phba);
if (rc)
mb = &pmbox->mb;
status = MBX_SUCCESS;
+ if (phba->hba_state == LPFC_HBA_ERROR) {
+ spin_unlock_irqrestore(phba->host->host_lock, drvr_flag);
+
+ /* Mbox command <mbxCommand> cannot issue */
+ LOG_MBOX_CANNOT_ISSUE_DATA( phba, mb, psli, flag)
+ return (MBX_NOT_FINISHED);
+ }
+
if (psli->sli_flag & LPFC_SLI_MBOX_ACTIVE) {
/* Polling for a mbox command when another one is already active
* is not allowed in SLI. Also, the driver must have established
/* If we are not polling, we MUST be in SLI2 mode */
if (flag != MBX_POLL) {
- if (!(psli->sli_flag & LPFC_SLI2_ACTIVE)) {
+ if (!(psli->sli_flag & LPFC_SLI2_ACTIVE) &&
+ (mb->mbxCommand != MBX_KILL_BOARD)) {
psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
spin_unlock_irqrestore(phba->host->host_lock,
drvr_flag);
/* First copy command data to host SLIM area */
lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx, MAILBOX_CMD_SIZE);
} else {
- if (mb->mbxCommand == MBX_CONFIG_PORT) {
+ if (mb->mbxCommand == MBX_CONFIG_PORT ||
+ mb->mbxCommand == MBX_KILL_BOARD) {
/* copy command data into host mbox for cmpl */
lpfc_sli_pcimem_bcopy(mb, &phba->slim2p->mbx,
MAILBOX_CMD_SIZE);
ha_copy = readl(phba->HAregaddr);
/* Wait for command to complete */
- while (((word0 & OWN_CHIP) == OWN_CHIP)
- || !(ha_copy & HA_MBATT)) {
+ while (((word0 & OWN_CHIP) == OWN_CHIP) ||
+ (!(ha_copy & HA_MBATT) &&
+ (phba->hba_state > LPFC_WARM_START))) {
if (i++ >= 100) {
psli->sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
spin_unlock_irqrestore(phba->host->host_lock,
!(phba->sli.sli_flag & LPFC_PROCESS_LA)))
goto iocb_busy;
- /*
- * Check to see if this is a high priority command.
- * If so bypass tx queue processing.
- */
- if (unlikely((flag & SLI_IOCB_HIGH_PRIORITY) &&
- (iocb = lpfc_sli_next_iocb_slot(phba, pring)))) {
- lpfc_sli_submit_iocb(phba, pring, iocb, piocb);
- piocb = NULL;
- }
-
while ((iocb = lpfc_sli_next_iocb_slot(phba, pring)) &&
(nextiocb = lpfc_sli_next_iocb(phba, pring, &piocb)))
lpfc_sli_submit_iocb(phba, pring, iocb, nextiocb);
return IOCB_BUSY;
}
+static int
+lpfc_extra_ring_setup( struct lpfc_hba *phba)
+{
+ struct lpfc_sli *psli;
+ struct lpfc_sli_ring *pring;
+
+ psli = &phba->sli;
+
+ /* Adjust cmd/rsp ring iocb entries more evenly */
+ pring = &psli->ring[psli->fcp_ring];
+ pring->numCiocb -= SLI2_IOCB_CMD_R1XTRA_ENTRIES;
+ pring->numRiocb -= SLI2_IOCB_RSP_R1XTRA_ENTRIES;
+ pring->numCiocb -= SLI2_IOCB_CMD_R3XTRA_ENTRIES;
+ pring->numRiocb -= SLI2_IOCB_RSP_R3XTRA_ENTRIES;
+
+ pring = &psli->ring[1];
+ pring->numCiocb += SLI2_IOCB_CMD_R1XTRA_ENTRIES;
+ pring->numRiocb += SLI2_IOCB_RSP_R1XTRA_ENTRIES;
+ pring->numCiocb += SLI2_IOCB_CMD_R3XTRA_ENTRIES;
+ pring->numRiocb += SLI2_IOCB_RSP_R3XTRA_ENTRIES;
+
+ /* Setup default profile for this ring */
+ pring->iotag_max = 4096;
+ pring->num_mask = 1;
+ pring->prt[0].profile = 0; /* Mask 0 */
+ pring->prt[0].rctl = FC_UNSOL_DATA;
+ pring->prt[0].type = 5;
+ pring->prt[0].lpfc_sli_rcv_unsol_event = NULL;
+ return 0;
+}
+
int
lpfc_sli_setup(struct lpfc_hba *phba)
{
"SLI2 SLIM Data: x%x x%x\n",
phba->brd_no, totiocb, MAX_SLI2_IOCB);
}
+ if (phba->cfg_multi_ring_support == 2)
+ lpfc_extra_ring_setup(phba);
return 0;
}
INIT_LIST_HEAD(&(pring->txq));
- if (pring->fast_lookup) {
- kfree(pring->fast_lookup);
- pring->fast_lookup = NULL;
- }
-
+ kfree(pring->fast_lookup);
+ pring->fast_lookup = NULL;
}
spin_unlock_irqrestore(phba->host->host_lock, flags);
spin_unlock_irqrestore(phba->host->host_lock, flags);
- /*
- * Provided the hba is not in an error state, reset it. It is not
- * capable of IO anymore.
- */
- if (phba->hba_state != LPFC_HBA_ERROR) {
- phba->hba_state = LPFC_INIT_START;
- lpfc_sli_brdreset(phba, 1);
- }
-
return 1;
}
struct lpfc_sli_ring * pring,
struct lpfc_iocbq * cmdiocb)
{
- struct list_head *lpfc_iocb_list = &phba->lpfc_iocb_list;
- struct lpfc_iocbq *abtsiocbp = NULL;
+ struct lpfc_iocbq *abtsiocbp;
IOCB_t *icmd = NULL;
IOCB_t *iabt = NULL;
/* issue ABTS for this IOCB based on iotag */
- list_remove_head(lpfc_iocb_list, abtsiocbp, struct lpfc_iocbq, list);
+ abtsiocbp = lpfc_sli_get_iocbq(phba);
if (abtsiocbp == NULL)
return 0;
}
static int
-lpfc_sli_validate_iocb_cmd(struct lpfc_scsi_buf *lpfc_cmd, uint16_t tgt_id,
- uint64_t lun_id, struct lpfc_iocbq *iocb,
- uint32_t ctx, lpfc_ctx_cmd ctx_cmd)
+lpfc_sli_validate_fcp_iocb(struct lpfc_iocbq *iocbq, uint16_t tgt_id,
+ uint64_t lun_id, uint32_t ctx,
+ lpfc_ctx_cmd ctx_cmd)
{
+ struct lpfc_scsi_buf *lpfc_cmd;
+ struct scsi_cmnd *cmnd;
int rc = 1;
- if (lpfc_cmd == NULL)
+ if (!(iocbq->iocb_flag & LPFC_IO_FCP))
+ return rc;
+
+ lpfc_cmd = container_of(iocbq, struct lpfc_scsi_buf, cur_iocbq);
+ cmnd = lpfc_cmd->pCmd;
+
+ if (cmnd == NULL)
return rc;
switch (ctx_cmd) {
case LPFC_CTX_LUN:
- if ((lpfc_cmd->pCmd->device->id == tgt_id) &&
- (lpfc_cmd->pCmd->device->lun == lun_id))
+ if ((cmnd->device->id == tgt_id) &&
+ (cmnd->device->lun == lun_id))
rc = 0;
break;
case LPFC_CTX_TGT:
- if (lpfc_cmd->pCmd->device->id == tgt_id)
+ if (cmnd->device->id == tgt_id)
rc = 0;
break;
case LPFC_CTX_CTX:
- if (iocb->iocb.ulpContext == ctx)
+ if (iocbq->iocb.ulpContext == ctx)
rc = 0;
+ break;
case LPFC_CTX_HOST:
rc = 0;
break;
lpfc_sli_sum_iocb(struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
uint16_t tgt_id, uint64_t lun_id, lpfc_ctx_cmd ctx_cmd)
{
- struct lpfc_iocbq *iocb, *next_iocb;
- IOCB_t *cmd = NULL;
- struct lpfc_scsi_buf *lpfc_cmd;
- int sum = 0, ret_val = 0;
+ struct lpfc_iocbq *iocbq;
+ int sum, i;
- /* Next check the txcmplq */
- list_for_each_entry_safe(iocb, next_iocb, &pring->txcmplq, list) {
- cmd = &iocb->iocb;
+ for (i = 1, sum = 0; i <= phba->sli.last_iotag; i++) {
+ iocbq = phba->sli.iocbq_lookup[i];
- /* Must be a FCP command */
- if ((cmd->ulpCommand != CMD_FCP_ICMND64_CR) &&
- (cmd->ulpCommand != CMD_FCP_IWRITE64_CR) &&
- (cmd->ulpCommand != CMD_FCP_IREAD64_CR)) {
- continue;
- }
-
- /* context1 MUST be a struct lpfc_scsi_buf */
- lpfc_cmd = (struct lpfc_scsi_buf *) (iocb->context1);
- ret_val = lpfc_sli_validate_iocb_cmd(lpfc_cmd, tgt_id, lun_id,
- NULL, 0, ctx_cmd);
- if (ret_val != 0)
- continue;
- sum++;
+ if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
+ 0, ctx_cmd) == 0)
+ sum++;
}
+
return sum;
}
uint16_t tgt_id, uint64_t lun_id, uint32_t ctx,
lpfc_ctx_cmd abort_cmd)
{
- struct lpfc_iocbq *iocb, *next_iocb;
- struct lpfc_iocbq *abtsiocb = NULL;
- struct list_head *lpfc_iocb_list = &phba->lpfc_iocb_list;
+ struct lpfc_iocbq *iocbq;
+ struct lpfc_iocbq *abtsiocb;
IOCB_t *cmd = NULL;
- struct lpfc_scsi_buf *lpfc_cmd;
int errcnt = 0, ret_val = 0;
+ int i;
- list_for_each_entry_safe(iocb, next_iocb, &pring->txcmplq, list) {
- cmd = &iocb->iocb;
-
- /* Must be a FCP command */
- if ((cmd->ulpCommand != CMD_FCP_ICMND64_CR) &&
- (cmd->ulpCommand != CMD_FCP_IWRITE64_CR) &&
- (cmd->ulpCommand != CMD_FCP_IREAD64_CR)) {
- continue;
- }
+ for (i = 1; i <= phba->sli.last_iotag; i++) {
+ iocbq = phba->sli.iocbq_lookup[i];
- /* context1 MUST be a struct lpfc_scsi_buf */
- lpfc_cmd = (struct lpfc_scsi_buf *) (iocb->context1);
- ret_val = lpfc_sli_validate_iocb_cmd(lpfc_cmd, tgt_id, lun_id,
- iocb, ctx, abort_cmd);
- if (ret_val != 0)
+ if (lpfc_sli_validate_fcp_iocb (iocbq, tgt_id, lun_id,
+ 0, abort_cmd) != 0)
continue;
/* issue ABTS for this IOCB based on iotag */
- list_remove_head(lpfc_iocb_list, abtsiocb, struct lpfc_iocbq,
- list);
+ abtsiocb = lpfc_sli_get_iocbq(phba);
if (abtsiocb == NULL) {
errcnt++;
continue;
}
+ cmd = &iocbq->iocb;
abtsiocb->iocb.un.acxri.abortType = ABORT_TYPE_ABTS;
abtsiocb->iocb.un.acxri.abortContextTag = cmd->ulpContext;
abtsiocb->iocb.un.acxri.abortIoTag = cmd->ulpIoTag;
return errcnt;
}
-void
-lpfc_sli_wake_iocb_high_priority(struct lpfc_hba * phba,
- struct lpfc_iocbq * queue1,
- struct lpfc_iocbq * queue2)
+static void
+lpfc_sli_wake_iocb_wait(struct lpfc_hba *phba,
+ struct lpfc_iocbq *cmdiocbq,
+ struct lpfc_iocbq *rspiocbq)
{
- struct lpfc_iocbq *save_iocbq = queue1->context2;
- if (save_iocbq && queue2)
- memcpy(&save_iocbq->iocb, &queue2->iocb, sizeof(queue2->iocb));
+ wait_queue_head_t *pdone_q;
+ unsigned long iflags;
+
+ spin_lock_irqsave(phba->host->host_lock, iflags);
+ cmdiocbq->iocb_flag |= LPFC_IO_WAKE;
+ if (cmdiocbq->context2 && rspiocbq)
+ memcpy(&((struct lpfc_iocbq *)cmdiocbq->context2)->iocb,
+ &rspiocbq->iocb, sizeof(IOCB_t));
- /* The waiter is looking for LPFC_IO_HIPRI bit to be set
- as a signal to wake up */
- queue1->iocb_flag |= LPFC_IO_HIPRI;
+ pdone_q = cmdiocbq->context_un.wait_queue;
+ spin_unlock_irqrestore(phba->host->host_lock, iflags);
+ if (pdone_q)
+ wake_up(pdone_q);
return;
}
+/*
+ * Issue the caller's iocb and wait for its completion, but no longer than the
+ * caller's timeout. Note that iocb_flags is cleared before the
+ * lpfc_sli_issue_call since the wake routine sets a unique value and by
+ * definition this is a wait function.
+ */
int
-lpfc_sli_issue_iocb_wait_high_priority(struct lpfc_hba * phba,
- struct lpfc_sli_ring * pring,
- struct lpfc_iocbq * piocb,
- uint32_t flag,
- struct lpfc_iocbq * prspiocbq,
- uint32_t timeout)
+lpfc_sli_issue_iocb_wait(struct lpfc_hba * phba,
+ struct lpfc_sli_ring * pring,
+ struct lpfc_iocbq * piocb,
+ struct lpfc_iocbq * prspiocbq,
+ uint32_t timeout)
{
- int j, delay_time, retval = IOCB_ERROR;
-
- /* The caller must left context1 empty. */
- if (piocb->context_un.hipri_wait_queue != 0) {
- return IOCB_ERROR;
- }
+ DECLARE_WAIT_QUEUE_HEAD(done_q);
+ long timeleft, timeout_req = 0;
+ int retval = IOCB_SUCCESS;
+ uint32_t creg_val;
/*
- * If the caller has provided a response iocbq buffer, context2 must
- * be NULL or its an error.
+ * If the caller has provided a response iocbq buffer, then context2
+ * is NULL or its an error.
*/
- if (prspiocbq && piocb->context2) {
- return IOCB_ERROR;
+ if (prspiocbq) {
+ if (piocb->context2)
+ return IOCB_ERROR;
+ piocb->context2 = prspiocbq;
}
- piocb->context2 = prspiocbq;
+ piocb->iocb_cmpl = lpfc_sli_wake_iocb_wait;
+ piocb->context_un.wait_queue = &done_q;
+ piocb->iocb_flag &= ~LPFC_IO_WAKE;
- /* Setup callback routine and issue the command. */
- piocb->iocb_cmpl = lpfc_sli_wake_iocb_high_priority;
- retval = lpfc_sli_issue_iocb(phba, pring, piocb,
- flag | SLI_IOCB_HIGH_PRIORITY);
- if (retval != IOCB_SUCCESS) {
- piocb->context2 = NULL;
- return IOCB_ERROR;
+ if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
+ creg_val = readl(phba->HCregaddr);
+ creg_val |= (HC_R0INT_ENA << LPFC_FCP_RING);
+ writel(creg_val, phba->HCregaddr);
+ readl(phba->HCregaddr); /* flush */
}
- /*
- * This high-priority iocb was sent out-of-band. Poll for its
- * completion rather than wait for a signal. Note that the host_lock
- * is held by the midlayer and must be released here to allow the
- * interrupt handlers to complete the IO and signal this routine via
- * the iocb_flag.
- * Also, the delay_time is computed to be one second longer than
- * the scsi command timeout to give the FW time to abort on
- * timeout rather than the driver just giving up. Typically,
- * the midlayer does not specify a time for this command so the
- * driver is free to enforce its own timeout.
- */
+ retval = lpfc_sli_issue_iocb(phba, pring, piocb, 0);
+ if (retval == IOCB_SUCCESS) {
+ timeout_req = timeout * HZ;
+ spin_unlock_irq(phba->host->host_lock);
+ timeleft = wait_event_timeout(done_q,
+ piocb->iocb_flag & LPFC_IO_WAKE,
+ timeout_req);
+ spin_lock_irq(phba->host->host_lock);
- delay_time = ((timeout + 1) * 1000) >> 6;
- retval = IOCB_ERROR;
- spin_unlock_irq(phba->host->host_lock);
- for (j = 0; j < 64; j++) {
- msleep(delay_time);
- if (piocb->iocb_flag & LPFC_IO_HIPRI) {
- piocb->iocb_flag &= ~LPFC_IO_HIPRI;
- retval = IOCB_SUCCESS;
- break;
+ if (timeleft == 0) {
+ lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
+ "%d:0329 IOCB wait timeout error - no "
+ "wake response Data x%x\n",
+ phba->brd_no, timeout);
+ retval = IOCB_TIMEDOUT;
+ } else if (!(piocb->iocb_flag & LPFC_IO_WAKE)) {
+ lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
+ "%d:0330 IOCB wake NOT set, "
+ "Data x%x x%lx\n", phba->brd_no,
+ timeout, (timeleft / jiffies));
+ retval = IOCB_TIMEDOUT;
+ } else {
+ lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
+ "%d:0331 IOCB wake signaled\n",
+ phba->brd_no);
}
+ } else {
+ lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
+ "%d:0332 IOCB wait issue failed, Data x%x\n",
+ phba->brd_no, retval);
+ retval = IOCB_ERROR;
}
- spin_lock_irq(phba->host->host_lock);
- piocb->context2 = NULL;
+ if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
+ creg_val = readl(phba->HCregaddr);
+ creg_val &= ~(HC_R0INT_ENA << LPFC_FCP_RING);
+ writel(creg_val, phba->HCregaddr);
+ readl(phba->HCregaddr); /* flush */
+ }
+
+ if (prspiocbq)
+ piocb->context2 = NULL;
+
+ piocb->context_un.wait_queue = NULL;
+ piocb->iocb_cmpl = NULL;
return retval;
}
+
int
lpfc_sli_issue_mbox_wait(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq,
uint32_t timeout)
pmboxq->context1 = NULL;
/* if schedule_timeout returns 0, we timed out and were not
woken up */
- if (timeleft == 0) {
+ if ((timeleft == 0) || signal_pending(current))
retval = MBX_TIMEOUT;
- } else {
+ else
retval = MBX_SUCCESS;
- }
}
/* Clear Chip error bit */
writel(HA_ERATT, phba->HAregaddr);
readl(phba->HAregaddr); /* flush */
-
- /*
- * Reseting the HBA is the only reliable way
- * to shutdown interrupt when there is a
- * ERROR.
- */
- lpfc_sli_send_reset(phba, phba->hba_state);
}
spin_lock(phba->host->host_lock);
projects / linux-2.6-omap-h63xx.git / blobdiff