/*
* Aic79xx register and scratch ram definitions.
*
- * Copyright (c) 1994-2001 Justin T. Gibbs.
+ * Copyright (c) 1994-2001, 2004 Justin T. Gibbs.
* Copyright (c) 2000-2002 Adaptec Inc.
* All rights reserved.
*
*
* $FreeBSD$
*/
-VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#70 $"
+VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $"
/*
* This file is processed by the aic7xxx_asm utility for use in assembling
mvi MODE_PTR, MK_MODE(src, dst); \
}
-#define TOGGLE_DFF_MODE \
- if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
- call toggle_dff_mode_work_around; \
- } else { \
- xor MODE_PTR, MK_MODE(M_DFF1, M_DFF1); \
- }
-
#define RESTORE_MODE(mode) \
if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \
mov mode call set_mode_work_around; \
mvi SEQINTCODE, code; \
}
+/*
+ * Registers marked "dont_generate_debug_code" are not (yet) referenced
+ * from the driver code, and this keyword inhibit generation
+ * of debug code for them.
+ *
+ * REG_PRETTY_PRINT config will complain if dont_generate_debug_code
+ * is added to the register which is referenced in the driver.
+ * Unreferenced register with no dont_generate_debug_code will result
+ * in dead code. No warning is issued.
+ */
+
/*
* Mode Pointer
* Controls which of the 5, 512byte, address spaces should be used
field DST_MODE 0x70
field SRC_MODE 0x07
mode_pointer
+ dont_generate_debug_code
}
const SRC_MODE_SHIFT 0
SAW_HWERR,
BAD_SCB_STATUS
}
+ dont_generate_debug_code
}
/*
register CLRINT {
address 0x003
access_mode WO
+ count 19
field CLRHWERRINT 0x80 /* Rev B or greater */
field CLRBRKADRINT 0x40
field CLRSWTMINT 0x20
field CLRSEQINT 0x04
field CLRCMDINT 0x02
field CLRSPLTINT 0x01
+ dont_generate_debug_code
}
/*
field SQPARERR 0x08
field ILLOPCODE 0x04
field DSCTMOUT 0x02
+ dont_generate_debug_code
}
/*
register HCNTRL {
address 0x005
access_mode RW
+ count 12
field SEQ_RESET 0x80 /* Rev B or greater */
field POWRDN 0x40
field SWINT 0x10
field INTEN 0x02
field CHIPRST 0x01
field CHIPRSTACK 0x01
+ dont_generate_debug_code
}
/*
address 0x006
access_mode RW
size 2
+ count 2
+ dont_generate_debug_code
}
/*
register HESCB_QOFF {
address 0x008
access_mode RW
+ count 2
+ dont_generate_debug_code
}
/*
*/
register SEQINTSTAT {
address 0x00C
+ count 1
access_mode RO
field SEQ_SWTMRTO 0x10
field SEQ_SEQINT 0x08
field CLRSEQ_SCSIINT 0x04
field CLRSEQ_PCIINT 0x02
field CLRSEQ_SPLTINT 0x01
+ dont_generate_debug_code
}
/*
address 0x00E
access_mode RW
size 2
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_CCHAN
+ dont_generate_debug_code
}
/*
*/
register SESCB_QOFF {
address 0x012
+ count 2
access_mode RW
modes M_CCHAN
+ dont_generate_debug_code
}
/*
access_mode RW
modes M_CCHAN
size 2
+ dont_generate_debug_code
}
/*
SCB_QSIZE_8192,
SCB_QSIZE_16384
}
+ dont_generate_debug_code
}
/*
address 0x019
access_mode RW
modes M_DFF0, M_DFF1
+ count 11
field PRELOADEN 0x80
field SCSIENWRDIS 0x40 /* Rev B only. */
field SCSIEN 0x20
*/
register DSCOMMAND0 {
address 0x019
+ count 1
access_mode RW
modes M_CFG
field CACHETHEN 0x80 /* Cache Threshold enable */
field EXTREQLCK 0x10 /* External Request Lock */
field DISABLE_TWATE 0x02 /* Rev B or greater */
field CIOPARCKEN 0x01 /* Internal bus parity error enable */
+ dont_generate_debug_code
}
/*
field SG_ADDR_MASK 0xf8
field ODD_SEG 0x04
field LAST_SEG 0x02
+ dont_generate_debug_code
}
register SG_CACHE_SHADOW {
access_mode RW
size 8
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
access_mode RW
size 3
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
access_mode RW
size 8
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
access_mode RW
size 8
modes M_CCHAN
+ dont_generate_debug_code
}
/*
address 0x084
access_mode RW
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
address 0x084
access_mode RW
modes M_CCHAN
+ dont_generate_debug_code
}
/*
address 0x088
access_mode RW
modes M_CFG
+ count 1
field WR_DFTHRSH 0x70 {
WR_DFTHRSH_MIN,
WR_DFTHRSH_25,
RD_DFTHRSH_90,
RD_DFTHRSH_MAX
}
+ dont_generate_debug_code
}
/*
address 0x093
access_mode RW
modes M_CFG
+ count 1
field SERRPULSE 0x80
field UNEXPSCIEN 0x20
field SPLTSMADIS 0x10
field SRSPDPEEN 0x04
field TSCSERREN 0x02
field CMPABCDIS 0x01
+ dont_generate_debug_code
}
/*
address 0x096
access_mode RW
modes M_DFF0, M_DFF1
+ count 2
field STAETERM 0x80
field SCBCERR 0x40
field SCADERR 0x20
field RXOVRUN 0x04
field RXSCEMSG 0x02
field RXSPLTRSP 0x01
+ dont_generate_debug_code
}
/*
address 0x097
access_mode RW
modes M_DFF0, M_DFF1
+ count 2
field RXDATABUCKET 0x01
+ dont_generate_debug_code
}
/*
address 0x09E
access_mode RW
modes M_DFF0, M_DFF1
+ count 2
field STAETERM 0x80
field SCBCERR 0x40
field SCADERR 0x20
field RXOVRUN 0x04
field RXSCEMSG 0x02
field RXSPLTRSP 0x01
+ dont_generate_debug_code
}
/*
address 0x09F
access_mode RW
modes M_DFF0, M_DFF1
+ count 2
field RXDATABUCKET 0x01
+ dont_generate_debug_code
}
/*
modes M_CFG
field TEST_GROUP 0xF0
field TEST_NUM 0x0F
+ dont_generate_debug_code
}
/*
address 0x0A0
access_mode RW
modes M_CFG
+ count 1
field DPE 0x80
field SSE 0x40
field RMA 0x20
field RDPERR 0x04
field TWATERR 0x02
field DPR 0x01
+ dont_generate_debug_code
}
/*
address 0x0A7
access_mode RW
modes M_CFG
+ count 5
field DPE 0x80
field SSE 0x40
field STA 0x08
field TWATERR 0x02
+ dont_generate_debug_code
}
/*
* LQ Packet In
- * The last LQ Packet received
+ * The last LQ Packet recieved
*/
register LQIN {
address 0x020
access_mode RW
size 20
+ count 2
modes M_DFF0, M_DFF1, M_SCSI
+ dont_generate_debug_code
}
/*
address 0x022
access_mode RW
modes M_CFG
+ count 2
+ dont_generate_debug_code
}
/*
address 0x025
access_mode RW
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
address 0x026
access_mode RW
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
address 0x027
access_mode RW
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
address 0x028
access_mode RW
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
address 0x029
access_mode RW
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
address 0x02B
access_mode RW
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
address 0x02C
access_mode RW
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
address 0x030
access_mode RW
modes M_CFG
+ count 2
mask ILUNLEN 0x0F
mask TLUNLEN 0xF0
+ dont_generate_debug_code
}
const LUNLEN_SINGLE_LEVEL_LUN 0xF
address 0x031
access_mode RW
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
address 0x032
access_mode RW
modes M_CFG
+ count 9
+ dont_generate_debug_code
}
/*
address 0x033
access_mode RW
modes M_CFG
+ dont_generate_debug_code
}
/*
address 0x038
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
+ count 2
field PCI2PCI 0x04
field SINGLECMD 0x02
field ABORTPENDING 0x01
+ dont_generate_debug_code
}
/*
address 0x039
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
+ count 5
field LQIRETRY 0x80
field LQICONTINUE 0x40
field LQITOIDLE 0x20
field LQOCONTINUE 0x04
field LQOTOIDLE 0x02
field LQOPAUSE 0x01
+ dont_generate_debug_code
}
/*
address 0x03B
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
+ count 8
field MANUALCTL 0x40
field ENSELI 0x20
field ENRSELI 0x10
field DFPEXP 0x40
field BIOSCANCELEN 0x10
field SPIOEN 0x08
+ dont_generate_debug_code
}
/*
field ENSTIMER 0x04
field ACTNEGEN 0x02
field STPWEN 0x01
+ dont_generate_debug_code
}
/*
P_STATUS CDO|IOO,
P_MESGIN CDO|IOO|MSGO
}
+ dont_generate_debug_code
}
+/*
+ * SCSI Control Signal In
+ */
register SCSISIGI {
address 0x041
access_mode RO
access_mode RW
modes M_CFG
size 2
+ count 2
+ dont_generate_debug_code
}
/*
access_mode RW
modes M_DFF0, M_DFF1, M_SCSI
size 2
+ dont_generate_debug_code
}
/*
address 0x048
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
+ count 2
field CLKOUT 0x80
field TARGID 0x0F
+ dont_generate_debug_code
}
/*
field ENAB40 0x08 /* LVD transceiver active */
field ENAB20 0x04 /* SE/HVD transceiver active */
field SELWIDE 0x02
+ dont_generate_debug_code
}
/*
address 0x04A
access_mode RW
modes M_CFG
+ count 4
field BIOSCANCTL 0x80
field AUTOACKEN 0x40
field BIASCANCTL 0x20
field ENDGFORMCHK 0x04
field AUTO_MSGOUT_DE 0x02
mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE
+ dont_generate_debug_code
}
/*
field CLROVERRUN 0x04
field CLRSPIORDY 0x02
field CLRARBDO 0x01
+ dont_generate_debug_code
}
/*
address 0x04B
access_mode RW
modes M_CFG
+ count 8
field ENSELDO 0x40
field ENSELDI 0x20
field ENSELINGO 0x10
field CLRSCSIPERR 0x04
field CLRSTRB2FAST 0x02
field CLRREQINIT 0x01
+ dont_generate_debug_code
}
/*
field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */
field CLRSDONE 0x02 /* Modes 0 and 1 only */
field CLRDMADONE 0x01 /* Modes 0 and 1 only */
+ dont_generate_debug_code
}
/*
address 0x04E
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
+ count 3
field HIZERO 0x80
field HIPERR 0x40
field PREVPHASE 0x20
address 0x04E
access_mode RO
modes M_CFG
+ count 6
+ dont_generate_debug_code
}
/*
address 0x04F
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
+ count 1
}
/*
address 0x04F
access_mode RO
modes M_CFG
+ count 2
+ dont_generate_debug_code
}
/*
address 0x050
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
+ count 2
field LQIATNQAS 0x20
field LQICRCT1 0x10
field LQICRCT2 0x08
address 0x050
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
+ count 1
field CLRLQIATNQAS 0x20
field CLRLQICRCT1 0x10
field CLRLQICRCT2 0x08
field CLRLQIBADLQT 0x04
field CLRLQIATNLQ 0x02
field CLRLQIATNCMD 0x01
+ dont_generate_debug_code
}
/*
address 0x050
access_mode RW
modes M_CFG
+ count 3
field ENLQIATNQASK 0x20
field ENLQICRCT1 0x10
field ENLQICRCT2 0x08
field ENLQIBADLQT 0x04
field ENLQIATNLQ 0x02
field ENLQIATNCMD 0x01
+ dont_generate_debug_code
}
/*
address 0x051
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
+ count 3
field LQIPHASE_LQ 0x80
field LQIPHASE_NLQ 0x40
field LQIABORT 0x20
address 0x051
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
+ count 4
field CLRLQIPHASE_LQ 0x80
field CLRLQIPHASE_NLQ 0x40
field CLRLIQABORT 0x20
field CLRLQIBADLQI 0x04
field CLRLQIOVERI_LQ 0x02
field CLRLQIOVERI_NLQ 0x01
+ dont_generate_debug_code
}
/*
address 0x051
access_mode RW
modes M_CFG
+ count 4
field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */
field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */
field ENLIQABORT 0x20
field ENLQIBADLQI 0x04
field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */
field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */
+ dont_generate_debug_code
}
/*
address 0x053
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
+ count 3
field NTRAMPERR 0x02
field OSRAMPERR 0x01
}
address 0x053
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
+ count 3
field CLRNTRAMPERR 0x02
field CLROSRAMPERR 0x01
+ dont_generate_debug_code
}
/*
address 0x053
access_mode RW
modes M_CFG
+ count 4
field ENNTRAMPERR 0x02
field ENOSRAMPERR 0x01
+ dont_generate_debug_code
}
/*
address 0x054
access_mode RO
modes M_DFF0, M_DFF1, M_SCSI
+ count 2
field LQOTARGSCBPERR 0x10
field LQOSTOPT2 0x08
field LQOATNLQ 0x04
address 0x054
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
+ count 3
field CLRLQOTARGSCBPERR 0x10
field CLRLQOSTOPT2 0x08
field CLRLQOATNLQ 0x04
field CLRLQOATNPKT 0x02
field CLRLQOTCRC 0x01
+ dont_generate_debug_code
}
/*
address 0x054
access_mode RW
modes M_CFG
+ count 4
field ENLQOTARGSCBPERR 0x10
field ENLQOSTOPT2 0x08
field ENLQOATNLQ 0x04
field ENLQOATNPKT 0x02
field ENLQOTCRC 0x01
+ dont_generate_debug_code
}
/*
address 0x055
access_mode WO
modes M_DFF0, M_DFF1, M_SCSI
+ count 7
field CLRLQOINITSCBPERR 0x10
field CLRLQOSTOPI2 0x08
field CLRLQOBADQAS 0x04
field CLRLQOBUSFREE 0x02
field CLRLQOPHACHGINPKT 0x01
+ dont_generate_debug_code
}
/*
address 0x055
access_mode RW
modes M_CFG
+ count 4
field ENLQOINITSCBPERR 0x10
field ENLQOSTOPI2 0x08
field ENLQOBADQAS 0x04
field ENLQOBUSFREE 0x02
field ENLQOPHACHGINPKT 0x01
+ dont_generate_debug_code
}
/*
address 0x056
access_mode RO
modes M_CFG
+ count 2
+ dont_generate_debug_code
}
/*
access_mode RO
size 2
modes M_DFF0, M_DFF1, M_SCSI
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_SCSI
+ dont_generate_debug_code
}
-/* Rev B only. */
+/*
+ * LQO SCSI Control
+ * (Rev B only.)
+ */
register LQOSCSCTL {
address 0x05A
access_mode RW
size 1
modes M_CFG
+ count 1
field LQOH2A_VERSION 0x80
+ field LQOBUSETDLY 0x40
+ field LQONOHOLDLACK 0x02
field LQONOCHKOVER 0x01
+ dont_generate_debug_code
}
/*
field CLRCFG4TSTAT 0x04
field CLRCFG4ICMD 0x02
field CLRCFG4TCMD 0x01
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_SCSI
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_SCSI
+ dont_generate_debug_code
}
/*
access_mode RO
size 8
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
address 0x060
access_mode RW
modes M_SCSI
+ dont_generate_debug_code
}
/*
address 0x061
access_mode RW
modes M_SCSI
+ count 1
+ dont_generate_debug_code
}
/*
address 0x062
access_mode RW
modes M_SCSI
+ count 1
+ dont_generate_debug_code
}
/*
address 0x063
access_mode RW
modes M_SCSI
+ count 1
field PPROPT_PACE 0x08
field PPROPT_QAS 0x04
field PPROPT_DT 0x02
field PPROPT_IUT 0x01
+ dont_generate_debug_code
}
/*
field ENAUTOATNI 0x04
field ENAUTOATNO 0x02
field WIDEXFER 0x01
+ dont_generate_debug_code
}
/*
address 0x065
access_mode RW
modes M_SCSI
+ count 7
+ dont_generate_debug_code
}
+/*
+ * SCSI Check
+ * (Rev. B only)
+ */
register SCSCHKN {
address 0x066
access_mode RW
modes M_CFG
+ count 1
+ field BIDICHKDIS 0x80
field STSELSKIDDIS 0x40
field CURRFIFODEF 0x20
field WIDERESEN 0x10
field DFFACTCLR 0x04
field SHVALIDSTDIS 0x02
field LSTSGCLRDIS 0x01
+ dont_generate_debug_code
}
const AHD_ANNEXCOL_PER_DEV0 4
address 0x066
access_mode RW
modes M_SCSI
+ count 3
+ dont_generate_debug_code
}
/*
address 0x067
access_mode RW
modes M_SCSI
+ dont_generate_debug_code
}
/*
address 0x069
access_mode RW
modes M_SCSI
+ count 2
+ dont_generate_debug_code
}
/*
access_mode RW
size 3
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI
+ dont_generate_debug_code
}
/*
address 0x0AB
access_mode RW
modes M_CFG
+ count 1
field AUSCBPTR_EN 0x80
field SCBPTR_ADDR 0x38
field SCBPTR_OFF 0x07
+ dont_generate_debug_code
}
/*
address 0x0AC
access_mode RW
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
address 0x0AC
access_mode RW
modes M_CCHAN
+ dont_generate_debug_code
}
/*
address 0x0B0
access_mode RW
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
address 0x0B0
access_mode RW
modes M_CCHAN
+ dont_generate_debug_code
}
/*
address 0x0B8
access_mode RW
modes M_SCSI
+ count 2
+ dont_generate_debug_code
}
/*
address 0x0B9
access_mode RW
modes M_SCSI
+ count 7
field FLXARBACK 0x80
field FLXARBREQ 0x40
field BRDADDR 0x38
field BRDEN 0x04
field BRDRW 0x02
field BRDSTB 0x01
+ dont_generate_debug_code
}
/*
address 0x0BA
access_mode RW
modes M_SCSI
+ count 4
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_SCSI
+ count 4
+ dont_generate_debug_code
}
/*
address 0x0BE
access_mode RO
modes M_SCSI
+ count 1
field INIT_DONE 0x80
field SEEOPCODE 0x70
field LDALTID_L 0x08
field SEEARBACK 0x04
field SEEBUSY 0x02
field SEESTART 0x01
+ dont_generate_debug_code
}
/*
address 0x0BE
access_mode RW
modes M_SCSI
+ count 4
field SEEOPCODE 0x70 {
SEEOP_ERASE 0x70,
SEEOP_READ 0x60,
mask SEEOP_EWDS 0x40
field SEERST 0x02
field SEESTART 0x01
+ dont_generate_debug_code
}
const SEEOP_ERAL_ADDR 0x80
address 0x0BF
access_mode RW
modes M_SCSI
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
address 0x0C1
access_mode RW
modes M_CFG
+ count 3
field BYPASSENAB 0x80
field DESQDIS 0x10
field RCVROFFSTDIS 0x04
field XMITOFFSTDIS 0x02
+ dont_generate_debug_code
}
/*
address 0x0C4
access_mode RW
modes M_DFF0, M_DFF1
+ dont_generate_debug_code
}
/*
address 0x0C4
access_mode RW
modes M_CFG
+ count 1
field AUTOINCEN 0x80
field DSPSEL 0x1F
+ dont_generate_debug_code
}
const NUMDSPS 0x14
address 0x0C5
access_mode WO
modes M_CFG
+ count 3
field AUTOXBCDIS 0x80
field XMITMANVAL 0x3F
+ dont_generate_debug_code
}
/*
*/
register SEQCTL0 {
address 0x0D6
- access_mode RW
+ access_mode RW
+ count 11
field PERRORDIS 0x80
field PAUSEDIS 0x40
field FAILDIS 0x20
*/
register FLAGS {
address 0x0D8
- access_mode RO
+ access_mode RO
+ count 23
field ZERO 0x02
field CARRY 0x01
+ dont_generate_debug_code
}
/*
*/
register SEQRAM {
address 0x0DA
- access_mode RW
+ access_mode RW
+ count 2
+ dont_generate_debug_code
}
/*
address 0x0DE
access_mode RW
size 2
+ count 5
+ dont_generate_debug_code
}
/*
*/
register ACCUM {
address 0x0E0
- access_mode RW
+ access_mode RW
accumulator
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
sindex
+ dont_generate_debug_code
}
/*
address 0x0E4
access_mode RW
size 2
+ dont_generate_debug_code
}
/*
address 0x0E8
access_mode RO
allones
+ dont_generate_debug_code
}
/*
address 0x0EA
access_mode RO
allzeros
+ dont_generate_debug_code
}
/*
address 0x0EA
access_mode WO
none
+ dont_generate_debug_code
}
/*
register SINDIR {
address 0x0EC
access_mode RO
+ dont_generate_debug_code
}
/*
register DINDIR {
address 0x0ED
access_mode WO
+ dont_generate_debug_code
}
/*
register STACK {
address 0x0F2
access_mode RW
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_SCSI
+ count 2
+ dont_generate_debug_code
}
/*
access_mode RW
size 2
modes M_CFG
+ count 1
+ dont_generate_debug_code
}
/*
modes 0, 1, 2, 3
REG0 {
size 2
+ dont_generate_debug_code
}
REG1 {
size 2
}
REG_ISR {
size 2
+ dont_generate_debug_code
}
SG_STATE {
size 1
modes 0, 1, 2, 3
LONGJMP_ADDR {
size 2
+ dont_generate_debug_code
}
ACCUM_SAVE {
size 1
+ dont_generate_debug_code
}
}
*/
WAITING_SCB_TAILS {
size 32
+ dont_generate_debug_code
}
WAITING_TID_HEAD {
size 2
+ dont_generate_debug_code
}
WAITING_TID_TAIL {
size 2
+ dont_generate_debug_code
}
/*
* SCBID of the next SCB in the new SCB queue.
*/
NEXT_QUEUED_SCB_ADDR {
size 4
+ dont_generate_debug_code
}
/*
* head of list of SCBs that have
*/
COMPLETE_SCB_HEAD {
size 2
+ dont_generate_debug_code
}
/*
* The list of completed SCBs in
*/
COMPLETE_SCB_DMAINPROG_HEAD {
size 2
+ dont_generate_debug_code
}
/*
* head of list of SCBs that have
*/
COMPLETE_DMA_SCB_HEAD {
size 2
+ dont_generate_debug_code
+ }
+ /*
+ * tail of list of SCBs that have
+ * completed but need to be uploaded
+ * to the host prior to being completed.
+ */
+ COMPLETE_DMA_SCB_TAIL {
+ size 2
+ dont_generate_debug_code
}
- /* Counting semaphore to prevent new select-outs */
+ /*
+ * head of list of SCBs that have
+ * been uploaded to the host, but cannot
+ * be completed until the QFREEZE is in
+ * full effect (i.e. no selections pending).
+ */
+ COMPLETE_ON_QFREEZE_HEAD {
+ size 2
+ dont_generate_debug_code
+ }
+ /*
+ * Counting semaphore to prevent new select-outs
+ * The queue is frozen so long as the sequencer
+ * and kernel freeze counts differ.
+ */
QFREEZE_COUNT {
size 2
}
+ KERNEL_QFREEZE_COUNT {
+ size 2
+ }
/*
* Mode to restore on legacy idle loop exit.
*/
*/
MSG_OUT {
size 1
+ dont_generate_debug_code
}
/* Parameters for DMA Logic */
DMAPARAMS {
size 1
+ count 8
field PRELOADEN 0x80
field WIDEODD 0x40
field SCSIEN 0x20
field DIRECTION 0x04 /* Set indicates PCI->SCSI */
field FIFOFLUSH 0x02
field FIFORESET 0x01
+ dont_generate_debug_code
}
SEQ_FLAGS {
size 1
*/
SAVED_SCSIID {
size 1
+ dont_generate_debug_code
}
SAVED_LUN {
size 1
+ dont_generate_debug_code
}
/*
* The last bus phase as seen by the sequencer.
*/
QOUTFIFO_ENTRY_VALID_TAG {
size 1
+ dont_generate_debug_code
+ }
+ /*
+ * Kernel and sequencer offsets into the queue of
+ * incoming target mode command descriptors. The
+ * queue is full when the KERNEL_TQINPOS == TQINPOS.
+ */
+ KERNEL_TQINPOS {
+ size 1
+ count 1
+ dont_generate_debug_code
+ }
+ TQINPOS {
+ size 1
+ count 8
+ dont_generate_debug_code
}
/*
* Base address of our shared data with the kernel driver in host
*/
SHARED_DATA_ADDR {
size 4
+ dont_generate_debug_code
}
/*
* Pointer to location in host memory for next
*/
QOUTFIFO_NEXT_ADDR {
size 4
- }
- /*
- * Kernel and sequencer offsets into the queue of
- * incoming target mode command descriptors. The
- * queue is full when the KERNEL_TQINPOS == TQINPOS.
- */
- KERNEL_TQINPOS {
- size 1
- }
- TQINPOS {
- size 1
+ dont_generate_debug_code
}
ARG_1 {
size 1
mask CONT_MSG_LOOP_READ 0x03
mask CONT_MSG_LOOP_TARG 0x02
alias RETURN_1
+ dont_generate_debug_code
}
ARG_2 {
size 1
+ count 1
alias RETURN_2
+ dont_generate_debug_code
}
/*
*/
LAST_MSG {
size 1
+ dont_generate_debug_code
}
/*
*/
SCSISEQ_TEMPLATE {
size 1
+ count 7
field MANUALCTL 0x40
field ENSELI 0x20
field ENRSELI 0x10
field MANUALP 0x0C
field ENAUTOATNP 0x02
field ALTSTIM 0x01
+ dont_generate_debug_code
}
/*
*/
INITIATOR_TAG {
size 1
+ count 1
+ dont_generate_debug_code
}
SEQ_FLAGS2 {
size 1
- field TARGET_MSG_PENDING 0x02
- field SELECTOUT_QFROZEN 0x04
+ field PENDING_MK_MESSAGE 0x01
+ field TARGET_MSG_PENDING 0x02
+ field SELECTOUT_QFROZEN 0x04
}
ALLOCFIFO_SCBPTR {
size 2
+ dont_generate_debug_code
}
/*
*/
INT_COALESCING_TIMER {
size 2
+ dont_generate_debug_code
}
/*
*/
INT_COALESCING_MAXCMDS {
size 1
+ dont_generate_debug_code
}
/*
*/
INT_COALESCING_MINCMDS {
size 1
+ dont_generate_debug_code
}
/*
*/
CMDS_PENDING {
size 2
+ dont_generate_debug_code
}
/*
*/
INT_COALESCING_CMDCOUNT {
size 1
+ dont_generate_debug_code
}
/*
*/
LOCAL_HS_MAILBOX {
size 1
+ dont_generate_debug_code
}
/*
* Target-mode CDB type to CDB length table used
*/
CMDSIZE_TABLE {
size 8
+ count 8
+ dont_generate_debug_code
+ }
+ /*
+ * When an SCB with the MK_MESSAGE flag is
+ * queued to the controller, it cannot enter
+ * the waiting for selection list until the
+ * selections for any previously queued
+ * commands to that target complete. During
+ * the wait, the MK_MESSAGE SCB is queued
+ * here.
+ */
+ MK_MESSAGE_SCB {
+ size 2
+ }
+ /*
+ * Saved SCSIID of MK_MESSAGE_SCB to avoid
+ * an extra SCBPTR operation when deciding
+ * if the MK_MESSAGE_SCB can be run.
+ */
+ MK_MESSAGE_SCSIID {
+ size 1
}
}
/************************* Hardware SCB Definition ****************************/
scb {
address 0x180
- size 64
- modes 0, 1, 2, 3
+ size 64
+ modes 0, 1, 2, 3
SCB_RESIDUAL_DATACNT {
size 4
alias SCB_CDB_STORE
alias SCB_HOST_CDB_PTR
+ dont_generate_debug_code
}
SCB_RESIDUAL_SGPTR {
size 4
field SG_ADDR_MASK 0xf8 /* In the last byte */
field SG_OVERRUN_RESID 0x02 /* In the first byte */
field SG_LIST_NULL 0x01 /* In the first byte */
+ dont_generate_debug_code
}
SCB_SCSI_STATUS {
size 1
alias SCB_HOST_CDB_LEN
+ dont_generate_debug_code
}
SCB_TARGET_PHASES {
size 1
+ dont_generate_debug_code
}
SCB_TARGET_DATA_DIR {
size 1
+ dont_generate_debug_code
}
SCB_TARGET_ITAG {
size 1
+ dont_generate_debug_code
}
SCB_SENSE_BUSADDR {
/*
*/
size 4
alias SCB_NEXT_COMPLETE
+ dont_generate_debug_code
}
SCB_TAG {
alias SCB_FIFO_USE_COUNT
size 2
+ dont_generate_debug_code
}
SCB_CONTROL {
size 1
SCB_LUN {
size 1
field LID 0xff
+ dont_generate_debug_code
}
SCB_TASK_ATTRIBUTE {
size 1
* ignore wide residue message handling.
*/
field SCB_XFERLEN_ODD 0x01
+ dont_generate_debug_code
}
SCB_CDB_LEN {
size 1
field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */
+ dont_generate_debug_code
}
SCB_TASK_MANAGEMENT {
size 1
+ dont_generate_debug_code
}
SCB_DATAPTR {
size 8
+ dont_generate_debug_code
}
SCB_DATACNT {
/*
size 4
field SG_LAST_SEG 0x80 /* In the fourth byte */
field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
+ dont_generate_debug_code
}
SCB_SGPTR {
size 4
field SG_STATUS_VALID 0x04 /* In the first byte */
field SG_FULL_RESID 0x02 /* In the first byte */
field SG_LIST_NULL 0x01 /* In the first byte */
+ dont_generate_debug_code
}
SCB_BUSADDR {
size 4
+ dont_generate_debug_code
}
SCB_NEXT {
alias SCB_NEXT_SCB_BUSADDR
size 2
+ dont_generate_debug_code
}
SCB_NEXT2 {
size 2
+ dont_generate_debug_code
}
SCB_SPARE {
size 8
}
SCB_DISCONNECTED_LISTS {
size 8
+ dont_generate_debug_code
}
}
const SG_SIZEOF download
const PKT_OVERRUN_BUFOFFSET download
const SCB_TRANSFER_SIZE download
+const CACHELINE_MASK download
/*
* BIOS SCB offsets
projects / linux-2.6-omap-h63xx.git / blobdiff