#include "shpchp.h"
-#ifdef DEBUG
-#define DBG_K_TRACE_ENTRY ((unsigned int)0x00000001) /* On function entry */
-#define DBG_K_TRACE_EXIT ((unsigned int)0x00000002) /* On function exit */
-#define DBG_K_INFO ((unsigned int)0x00000004) /* Info messages */
-#define DBG_K_ERROR ((unsigned int)0x00000008) /* Error messages */
-#define DBG_K_TRACE (DBG_K_TRACE_ENTRY|DBG_K_TRACE_EXIT)
-#define DBG_K_STANDARD (DBG_K_INFO|DBG_K_ERROR|DBG_K_TRACE)
-/* Redefine this flagword to set debug level */
-#define DEBUG_LEVEL DBG_K_STANDARD
-
-#define DEFINE_DBG_BUFFER char __dbg_str_buf[256];
-
-#define DBG_PRINT( dbg_flags, args... ) \
- do { \
- if ( DEBUG_LEVEL & ( dbg_flags ) ) \
- { \
- int len; \
- len = sprintf( __dbg_str_buf, "%s:%d: %s: ", \
- __FILE__, __LINE__, __FUNCTION__ ); \
- sprintf( __dbg_str_buf + len, args ); \
- printk( KERN_NOTICE "%s\n", __dbg_str_buf ); \
- } \
- } while (0)
-
-#define DBG_ENTER_ROUTINE DBG_PRINT (DBG_K_TRACE_ENTRY, "%s", "[Entry]");
-#define DBG_LEAVE_ROUTINE DBG_PRINT (DBG_K_TRACE_EXIT, "%s", "[Exit]");
-#else
-#define DEFINE_DBG_BUFFER
-#define DBG_ENTER_ROUTINE
-#define DBG_LEAVE_ROUTINE
-#endif /* DEBUG */
-
/* Slot Available Register I field definition */
#define SLOT_33MHZ 0x0000001f
#define SLOT_66MHZ_PCIX 0x00001f00
#define SLOT_EVENT_LATCH 0x2
#define SLOT_SERR_INT_MASK 0x3
-DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
static irqreturn_t shpc_isr(int irq, void *dev_id);
{
struct controller *ctrl = (struct controller *)data;
- DBG_ENTER_ROUTINE
-
/* Poll for interrupt events. regs == NULL => polling */
shpc_isr(0, ctrl);
shpchp_poll_time = 2; /* default polling interval is 2 sec */
start_int_poll_timer(ctrl, shpchp_poll_time);
-
- DBG_LEAVE_ROUTINE
}
/*
!is_ctrl_busy(ctrl), timeout);
if (!rc && is_ctrl_busy(ctrl)) {
retval = -EIO;
- err("Command not completed in 1000 msec\n");
+ ctrl_err(ctrl, "Command not completed in 1000 msec\n");
} else if (rc < 0) {
retval = -EINTR;
- info("Command was interrupted by a signal\n");
+ ctrl_info(ctrl, "Command was interrupted by a signal\n");
}
return retval;
int retval = 0;
u16 temp_word;
- DBG_ENTER_ROUTINE
-
mutex_lock(&slot->ctrl->cmd_lock);
if (!shpc_poll_ctrl_busy(ctrl)) {
/* After 1 sec and and the controller is still busy */
- err("%s : Controller is still busy after 1 sec.\n",
- __FUNCTION__);
+ ctrl_err(ctrl, "Controller is still busy after 1 sec\n");
retval = -EBUSY;
goto out;
}
++t_slot;
temp_word = (t_slot << 8) | (cmd & 0xFF);
- dbg("%s: t_slot %x cmd %x\n", __FUNCTION__, t_slot, cmd);
-
+ ctrl_dbg(ctrl, "%s: t_slot %x cmd %x\n", __func__, t_slot, cmd);
+
/* To make sure the Controller Busy bit is 0 before we send out the
- * command.
+ * command.
*/
shpc_writew(ctrl, CMD, temp_word);
cmd_status = hpc_check_cmd_status(slot->ctrl);
if (cmd_status) {
- err("%s: Failed to issued command 0x%x (error code = %d)\n",
- __FUNCTION__, cmd, cmd_status);
+ ctrl_err(ctrl,
+ "Failed to issued command 0x%x (error code = %d)\n",
+ cmd, cmd_status);
retval = -EIO;
}
out:
mutex_unlock(&slot->ctrl->cmd_lock);
-
- DBG_LEAVE_ROUTINE
return retval;
}
static int hpc_check_cmd_status(struct controller *ctrl)
{
- u16 cmd_status;
int retval = 0;
+ u16 cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
- DBG_ENTER_ROUTINE
-
- cmd_status = shpc_readw(ctrl, CMD_STATUS) & 0x000F;
-
switch (cmd_status >> 1) {
case 0:
retval = 0;
break;
case 1:
retval = SWITCH_OPEN;
- err("%s: Switch opened!\n", __FUNCTION__);
+ ctrl_err(ctrl, "Switch opened!\n");
break;
case 2:
retval = INVALID_CMD;
- err("%s: Invalid HPC command!\n", __FUNCTION__);
+ ctrl_err(ctrl, "Invalid HPC command!\n");
break;
case 4:
retval = INVALID_SPEED_MODE;
- err("%s: Invalid bus speed/mode!\n", __FUNCTION__);
+ ctrl_err(ctrl, "Invalid bus speed/mode!\n");
break;
default:
retval = cmd_status;
}
- DBG_LEAVE_ROUTINE
return retval;
}
static int hpc_get_attention_status(struct slot *slot, u8 *status)
{
struct controller *ctrl = slot->ctrl;
- u32 slot_reg;
- u8 state;
-
- DBG_ENTER_ROUTINE
-
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
+ u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
+ u8 state = (slot_reg & ATN_LED_STATE_MASK) >> ATN_LED_STATE_SHIFT;
switch (state) {
case ATN_LED_STATE_ON:
break;
}
- DBG_LEAVE_ROUTINE
return 0;
}
static int hpc_get_power_status(struct slot * slot, u8 *status)
{
struct controller *ctrl = slot->ctrl;
- u32 slot_reg;
- u8 state;
-
- DBG_ENTER_ROUTINE
-
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
+ u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
+ u8 state = (slot_reg & SLOT_STATE_MASK) >> SLOT_STATE_SHIFT;
switch (state) {
case SLOT_STATE_PWRONLY:
break;
}
- DBG_LEAVE_ROUTINE
return 0;
}
static int hpc_get_latch_status(struct slot *slot, u8 *status)
{
struct controller *ctrl = slot->ctrl;
- u32 slot_reg;
-
- DBG_ENTER_ROUTINE
+ u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
*status = !!(slot_reg & MRL_SENSOR); /* 0 -> close; 1 -> open */
- DBG_LEAVE_ROUTINE
return 0;
}
static int hpc_get_adapter_status(struct slot *slot, u8 *status)
{
struct controller *ctrl = slot->ctrl;
- u32 slot_reg;
- u8 state;
-
- DBG_ENTER_ROUTINE
+ u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
+ u8 state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- state = (slot_reg & PRSNT_MASK) >> PRSNT_SHIFT;
*status = (state != 0x3) ? 1 : 0;
- DBG_LEAVE_ROUTINE
return 0;
}
{
struct controller *ctrl = slot->ctrl;
- DBG_ENTER_ROUTINE
-
*prog_int = shpc_readb(ctrl, PROG_INTERFACE);
- DBG_LEAVE_ROUTINE
return 0;
}
u8 m66_cap = !!(slot_reg & MHZ66_CAP);
u8 pi, pcix_cap;
- DBG_ENTER_ROUTINE
-
if ((retval = hpc_get_prog_int(slot, &pi)))
return retval;
return -ENODEV;
}
- dbg("%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
- __FUNCTION__, slot_reg, pcix_cap, m66_cap);
+ ctrl_dbg(ctrl, "%s: slot_reg = %x, pcix_cap = %x, m66_cap = %x\n",
+ __func__, slot_reg, pcix_cap, m66_cap);
switch (pcix_cap) {
case 0x0:
break;
}
- dbg("Adapter speed = %d\n", *value);
- DBG_LEAVE_ROUTINE
+ ctrl_dbg(ctrl, "Adapter speed = %d\n", *value);
return retval;
}
static int hpc_get_mode1_ECC_cap(struct slot *slot, u8 *mode)
{
- struct controller *ctrl = slot->ctrl;
- u16 sec_bus_status;
- u8 pi;
int retval = 0;
-
- DBG_ENTER_ROUTINE
-
- pi = shpc_readb(ctrl, PROG_INTERFACE);
- sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
+ struct controller *ctrl = slot->ctrl;
+ u16 sec_bus_status = shpc_readw(ctrl, SEC_BUS_CONFIG);
+ u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
if (pi == 2) {
*mode = (sec_bus_status & 0x0100) >> 8;
retval = -1;
}
- dbg("Mode 1 ECC cap = %d\n", *mode);
-
- DBG_LEAVE_ROUTINE
+ ctrl_dbg(ctrl, "Mode 1 ECC cap = %d\n", *mode);
return retval;
}
static int hpc_query_power_fault(struct slot * slot)
{
struct controller *ctrl = slot->ctrl;
- u32 slot_reg;
-
- DBG_ENTER_ROUTINE
-
- slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
+ u32 slot_reg = shpc_readl(ctrl, SLOT_REG(slot->hp_slot));
- DBG_LEAVE_ROUTINE
/* Note: Logic 0 => fault */
return !(slot_reg & POWER_FAULT);
}
u8 slot_cmd = 0;
switch (value) {
- case 0 :
+ case 0 :
slot_cmd = SET_ATTN_OFF; /* OFF */
break;
case 1:
int i;
u32 slot_reg, serr_int;
- DBG_ENTER_ROUTINE
-
/*
* Mask event interrupts and SERRs of all slots
*/
cleanup_slots(ctrl);
/*
- * Mask SERR and System Interrut generation
+ * Mask SERR and System Interrupt generation
*/
serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
serr_int |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
*/
if (atomic_dec_and_test(&shpchp_num_controllers))
destroy_workqueue(shpchp_wq);
-
- DBG_LEAVE_ROUTINE
}
static int hpc_power_on_slot(struct slot * slot)
{
int retval;
- DBG_ENTER_ROUTINE
-
retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
- if (retval) {
- err("%s: Write command failed!\n", __FUNCTION__);
- return retval;
- }
-
- DBG_LEAVE_ROUTINE
+ if (retval)
+ ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
- return 0;
+ return retval;
}
static int hpc_slot_enable(struct slot * slot)
{
int retval;
- DBG_ENTER_ROUTINE
-
/* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
retval = shpc_write_cmd(slot, slot->hp_slot,
SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
- if (retval) {
- err("%s: Write command failed!\n", __FUNCTION__);
- return retval;
- }
+ if (retval)
+ ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
- DBG_LEAVE_ROUTINE
- return 0;
+ return retval;
}
static int hpc_slot_disable(struct slot * slot)
{
int retval;
- DBG_ENTER_ROUTINE
-
/* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
retval = shpc_write_cmd(slot, slot->hp_slot,
SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
- if (retval) {
- err("%s: Write command failed!\n", __FUNCTION__);
- return retval;
- }
+ if (retval)
+ ctrl_err(slot->ctrl, "%s: Write command failed!\n", __func__);
- DBG_LEAVE_ROUTINE
- return 0;
+ return retval;
}
static int hpc_set_bus_speed_mode(struct slot * slot, enum pci_bus_speed value)
struct controller *ctrl = slot->ctrl;
u8 pi, cmd;
- DBG_ENTER_ROUTINE
-
pi = shpc_readb(ctrl, PROG_INTERFACE);
if ((pi == 1) && (value > PCI_SPEED_133MHz_PCIX))
return -EINVAL;
retval = shpc_write_cmd(slot, 0, cmd);
if (retval)
- err("%s: Write command failed!\n", __FUNCTION__);
+ ctrl_err(ctrl, "%s: Write command failed!\n", __func__);
- DBG_LEAVE_ROUTINE
return retval;
}
if (!intr_loc)
return IRQ_NONE;
- dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
+ ctrl_dbg(ctrl, "%s: intr_loc = %x\n", __func__, intr_loc);
if(!shpchp_poll_mode) {
/*
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
intr_loc2 = shpc_readl(ctrl, INTR_LOC);
- dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
+ ctrl_dbg(ctrl, "%s: intr_loc2 = %x\n", __func__, intr_loc2);
}
if (intr_loc & CMD_INTR_PENDING) {
- /*
- * Command Complete Interrupt Pending
+ /*
+ * Command Complete Interrupt Pending
* RO only - clear by writing 1 to the Command Completion
* Detect bit in Controller SERR-INT register
*/
if (!(intr_loc & ~CMD_INTR_PENDING))
goto out;
- for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
+ for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
/* To find out which slot has interrupt pending */
if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
continue;
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
- dbg("%s: Slot %x with intr, slot register = %x\n",
- __FUNCTION__, hp_slot, slot_reg);
+ ctrl_dbg(ctrl, "Slot %x with intr, slot register = %x\n",
+ hp_slot, slot_reg);
if (slot_reg & MRL_CHANGE_DETECTED)
shpchp_handle_switch_change(hp_slot, ctrl);
serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
}
-
+
return IRQ_HANDLED;
}
u32 slot_avail1 = shpc_readl(ctrl, SLOT_AVAIL1);
u32 slot_avail2 = shpc_readl(ctrl, SLOT_AVAIL2);
- DBG_ENTER_ROUTINE
-
if (pi == 2) {
if (slot_avail2 & SLOT_133MHZ_PCIX_533)
bus_speed = PCI_SPEED_133MHz_PCIX_533;
}
*value = bus_speed;
- dbg("Max bus speed = %d\n", bus_speed);
- DBG_LEAVE_ROUTINE
+ ctrl_dbg(ctrl, "Max bus speed = %d\n", bus_speed);
+
return retval;
}
u8 pi = shpc_readb(ctrl, PROG_INTERFACE);
u8 speed_mode = (pi == 2) ? (sec_bus_reg & 0xF) : (sec_bus_reg & 0x7);
- DBG_ENTER_ROUTINE
-
if ((pi == 1) && (speed_mode > 4)) {
*value = PCI_SPEED_UNKNOWN;
return -ENODEV;
break;
}
- dbg("Current bus speed = %d\n", bus_speed);
- DBG_LEAVE_ROUTINE
+ ctrl_dbg(ctrl, "Current bus speed = %d\n", bus_speed);
return retval;
}
.power_on_slot = hpc_power_on_slot,
.slot_enable = hpc_slot_enable,
.slot_disable = hpc_slot_disable,
- .set_bus_speed_mode = hpc_set_bus_speed_mode,
+ .set_bus_speed_mode = hpc_set_bus_speed_mode,
.set_attention_status = hpc_set_attention_status,
.get_power_status = hpc_get_power_status,
.get_attention_status = hpc_get_attention_status,
.green_led_on = hpc_set_green_led_on,
.green_led_off = hpc_set_green_led_off,
.green_led_blink = hpc_set_green_led_blink,
-
+
.release_ctlr = hpc_release_ctlr,
};
u32 tempdword, slot_reg, slot_config;
u8 i;
- DBG_ENTER_ROUTINE
-
ctrl->pci_dev = pdev; /* pci_dev of the P2P bridge */
+ ctrl_dbg(ctrl, "Hotplug Controller:\n");
if ((pdev->vendor == PCI_VENDOR_ID_AMD) || (pdev->device ==
PCI_DEVICE_ID_AMD_GOLAM_7450)) {
} else {
ctrl->cap_offset = pci_find_capability(pdev, PCI_CAP_ID_SHPC);
if (!ctrl->cap_offset) {
- err("%s : cap_offset == 0\n", __FUNCTION__);
+ ctrl_err(ctrl, "Cannot find PCI capability\n");
goto abort;
}
- dbg("%s: cap_offset = %x\n", __FUNCTION__, ctrl->cap_offset);
+ ctrl_dbg(ctrl, " cap_offset = %x\n", ctrl->cap_offset);
rc = shpc_indirect_read(ctrl, 0, &shpc_base_offset);
if (rc) {
- err("%s: cannot read base_offset\n", __FUNCTION__);
+ ctrl_err(ctrl, "Cannot read base_offset\n");
goto abort;
}
rc = shpc_indirect_read(ctrl, 3, &tempdword);
if (rc) {
- err("%s: cannot read slot config\n", __FUNCTION__);
+ ctrl_err(ctrl, "Cannot read slot config\n");
goto abort;
}
num_slots = tempdword & SLOT_NUM;
- dbg("%s: num_slots (indirect) %x\n", __FUNCTION__, num_slots);
+ ctrl_dbg(ctrl, " num_slots (indirect) %x\n", num_slots);
for (i = 0; i < 9 + num_slots; i++) {
rc = shpc_indirect_read(ctrl, i, &tempdword);
if (rc) {
- err("%s: cannot read creg (index = %d)\n",
- __FUNCTION__, i);
+ ctrl_err(ctrl,
+ "Cannot read creg (index = %d)\n", i);
goto abort;
}
- dbg("%s: offset %d: value %x\n", __FUNCTION__,i,
- tempdword);
+ ctrl_dbg(ctrl, " offset %d: value %x\n", i, tempdword);
}
ctrl->mmio_base =
ctrl->mmio_size = 0x24 + 0x4 * num_slots;
}
- info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
- pdev->subsystem_device);
-
+ ctrl_info(ctrl, "HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
+ pdev->vendor, pdev->device, pdev->subsystem_vendor,
+ pdev->subsystem_device);
+
rc = pci_enable_device(pdev);
if (rc) {
- err("%s: pci_enable_device failed\n", __FUNCTION__);
+ ctrl_err(ctrl, "pci_enable_device failed\n");
goto abort;
}
if (!request_mem_region(ctrl->mmio_base, ctrl->mmio_size, MY_NAME)) {
- err("%s: cannot reserve MMIO region\n", __FUNCTION__);
+ ctrl_err(ctrl, "Cannot reserve MMIO region\n");
rc = -1;
goto abort;
}
ctrl->creg = ioremap(ctrl->mmio_base, ctrl->mmio_size);
if (!ctrl->creg) {
- err("%s: cannot remap MMIO region %lx @ %lx\n", __FUNCTION__,
- ctrl->mmio_size, ctrl->mmio_base);
+ ctrl_err(ctrl, "Cannot remap MMIO region %lx @ %lx\n",
+ ctrl->mmio_size, ctrl->mmio_base);
release_mem_region(ctrl->mmio_base, ctrl->mmio_size);
rc = -1;
goto abort;
}
- dbg("%s: ctrl->creg %p\n", __FUNCTION__, ctrl->creg);
+ ctrl_dbg(ctrl, "ctrl->creg %p\n", ctrl->creg);
mutex_init(&ctrl->crit_sect);
mutex_init(&ctrl->cmd_lock);
/* Mask Global Interrupt Mask & Command Complete Interrupt Mask */
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
+ ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
tempdword |= (GLOBAL_INTR_MASK | GLOBAL_SERR_MASK |
COMMAND_INTR_MASK | ARBITER_SERR_MASK);
tempdword &= ~SERR_INTR_RSVDZ_MASK;
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
+ ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
/* Mask the MRL sensor SERR Mask of individual slot in
* Slot SERR-INT Mask & clear all the existing event if any
*/
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
- dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
- hp_slot, slot_reg);
+ ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
+ hp_slot, slot_reg);
slot_reg |= (PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
CON_PFAULT_INTR_MASK | MRL_CHANGE_SERR_MASK |
slot_reg &= ~SLOT_REG_RSVDZ_MASK;
shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
}
-
+
if (shpchp_poll_mode) {
/* Install interrupt polling timer. Start with 10 sec delay */
init_timer(&ctrl->poll_timer);
/* Installs the interrupt handler */
rc = pci_enable_msi(pdev);
if (rc) {
- info("Can't get msi for the hotplug controller\n");
- info("Use INTx for the hotplug controller\n");
+ ctrl_info(ctrl,
+ "Can't get msi for the hotplug controller\n");
+ ctrl_info(ctrl,
+ "Use INTx for the hotplug controller\n");
}
-
+
rc = request_irq(ctrl->pci_dev->irq, shpc_isr, IRQF_SHARED,
MY_NAME, (void *)ctrl);
- dbg("%s: request_irq %d for hpc%d (returns %d)\n",
- __FUNCTION__, ctrl->pci_dev->irq,
+ ctrl_dbg(ctrl, "request_irq %d for hpc%d (returns %d)\n",
+ ctrl->pci_dev->irq,
atomic_read(&shpchp_num_controllers), rc);
if (rc) {
- err("Can't get irq %d for the hotplug controller\n",
- ctrl->pci_dev->irq);
+ ctrl_err(ctrl, "Can't get irq %d for the hotplug "
+ "controller\n", ctrl->pci_dev->irq);
goto abort_iounmap;
}
}
- dbg("%s: HPC at b:d:f:irq=0x%x:%x:%x:%x\n", __FUNCTION__,
- pdev->bus->number, PCI_SLOT(pdev->devfn),
- PCI_FUNC(pdev->devfn), pdev->irq);
- get_hp_hw_control_from_firmware(pdev);
+ ctrl_dbg(ctrl, "HPC at %s irq=%x\n", pci_name(pdev), pdev->irq);
/*
* If this is the first controller to be initialized,
*/
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
- dbg("%s: Default Logical Slot Register %d value %x\n", __FUNCTION__,
- hp_slot, slot_reg);
+ ctrl_dbg(ctrl, "Default Logical Slot Register %d value %x\n",
+ hp_slot, slot_reg);
slot_reg &= ~(PRSNT_CHANGE_INTR_MASK | ISO_PFAULT_INTR_MASK |
BUTTON_PRESS_INTR_MASK | MRL_CHANGE_INTR_MASK |
CON_PFAULT_INTR_MASK | SLOT_REG_RSVDZ_MASK);
SERR_INTR_RSVDZ_MASK);
shpc_writel(ctrl, SERR_INTR_ENABLE, tempdword);
tempdword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- dbg("%s: SERR_INTR_ENABLE = %x\n", __FUNCTION__, tempdword);
+ ctrl_dbg(ctrl, "SERR_INTR_ENABLE = %x\n", tempdword);
}
- DBG_LEAVE_ROUTINE
return 0;
/* We end up here for the many possible ways to fail this API. */
abort_iounmap:
iounmap(ctrl->creg);
abort:
- DBG_LEAVE_ROUTINE
return rc;
}
projects / linux-2.6-omap-h63xx.git / blobdiff