]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - drivers/net/wireless/ath5k/reset.c
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/sam/kbuild...
[linux-2.6-omap-h63xx.git] / drivers / net / wireless / ath5k / reset.c
index f5c3de890cdbfb6e927ff9b6e871af8852a88d84..1b6d45b6772db39c269752e1b5bbef4e328d6389 100644 (file)
@@ -173,8 +173,10 @@ static int ath5k_hw_nic_reset(struct ath5k_hw *ah, u32 val)
        udelay(15);
 
        if (ah->ah_version == AR5K_AR5210) {
-               val &= AR5K_RESET_CTL_CHIP;
-               mask &= AR5K_RESET_CTL_CHIP;
+               val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
+                       | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
+               mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_DMA
+                       | AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_PHY;
        } else {
                val &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
                mask &= AR5K_RESET_CTL_PCU | AR5K_RESET_CTL_BASEBAND;
@@ -361,16 +363,20 @@ int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial)
        bus_flags = (pdev->is_pcie) ? 0 : AR5K_RESET_CTL_PCI;
 
        /* Reset chipset */
-       ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
-               AR5K_RESET_CTL_BASEBAND | bus_flags);
+       if (ah->ah_version == AR5K_AR5210) {
+               ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+                       AR5K_RESET_CTL_MAC | AR5K_RESET_CTL_DMA |
+                       AR5K_RESET_CTL_PHY | AR5K_RESET_CTL_PCI);
+                       mdelay(2);
+       } else {
+               ret = ath5k_hw_nic_reset(ah, AR5K_RESET_CTL_PCU |
+                       AR5K_RESET_CTL_BASEBAND | bus_flags);
+       }
        if (ret) {
                ATH5K_ERR(ah->ah_sc, "failed to reset the MAC Chip\n");
                return -EIO;
        }
 
-       if (ah->ah_version == AR5K_AR5210)
-               udelay(2300);
-
        /* ...wakeup again!*/
        ret = ath5k_hw_set_power(ah, AR5K_PM_AWAKE, true, 0);
        if (ret) {
@@ -531,19 +537,20 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                mdelay(1);
 
                /*
-                * Write some more initial register settings
+                * Write some more initial register settings for revised chips
                 */
-               if (ah->ah_version == AR5K_AR5212) {
+               if (ah->ah_version == AR5K_AR5212 &&
+                   ah->ah_phy_revision > 0x41) {
                        ath5k_hw_reg_write(ah, 0x0002a002, 0x982c);
 
                        if (channel->hw_value == CHANNEL_G)
-                               if (ah->ah_mac_srev < AR5K_SREV_VER_AR2413)
+                               if (ah->ah_mac_srev < AR5K_SREV_AR2413)
                                        ath5k_hw_reg_write(ah, 0x00f80d80,
                                                                0x994c);
-                               else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2424)
+                               else if (ah->ah_mac_srev < AR5K_SREV_AR5424)
                                        ath5k_hw_reg_write(ah, 0x00380140,
                                                                0x994c);
-                               else if (ah->ah_mac_srev < AR5K_SREV_VER_AR2425)
+                               else if (ah->ah_mac_srev < AR5K_SREV_AR2425)
                                        ath5k_hw_reg_write(ah, 0x00fc0ec0,
                                                                0x994c);
                                else /* 2425 */
@@ -552,19 +559,10 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                        else
                                ath5k_hw_reg_write(ah, 0x00000000, 0x994c);
 
-                       /* Some bits are disabled here, we know nothing about
-                        * register 0xa228 yet, most of the times this ends up
-                        * with a value 0x9b5 -haven't seen any dump with
-                        * a different value- */
-                       /* Got this from decompiling binary HAL */
-                       data = ath5k_hw_reg_read(ah, 0xa228);
-                       data &= 0xfffffdff;
-                       ath5k_hw_reg_write(ah, data, 0xa228);
-
-                       data = ath5k_hw_reg_read(ah, 0xa228);
-                       data &= 0xfffe03ff;
-                       ath5k_hw_reg_write(ah, data, 0xa228);
-                       data = 0;
+                       /* Got this from legacy-hal */
+                       AR5K_REG_DISABLE_BITS(ah, 0xa228, 0x200);
+
+                       AR5K_REG_MASKED_BITS(ah, 0xa228, 0x800, 0xfffe03ff);
 
                        /* Just write 0x9b5 ? */
                        /* ath5k_hw_reg_write(ah, 0x000009b5, 0xa228); */
@@ -909,7 +907,7 @@ int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode,
                ath5k_hw_reg_write(ah, 0x000100aa, 0x8118);
                ath5k_hw_reg_write(ah, 0x00003210, 0x811c);
                ath5k_hw_reg_write(ah, 0x00000052, 0x8108);
-               if (ah->ah_mac_srev >= AR5K_SREV_VER_AR2413)
+               if (ah->ah_mac_srev >= AR5K_SREV_AR2413)
                        ath5k_hw_reg_write(ah, 0x00000004, 0x8120);
        }