[TG3]: 40-bit DMA workaround part 2

[linux-2.6-omap-h63xx.git] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 2e733c60bfa40f497a991c89038f586b9cd85d50..7e3b613afb293f7c036b63b5ac1e174c24ca7a61 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -137,6 +137,7 @@
 #define   ASIC_REV_5750                         0x04
 #define   ASIC_REV_5752                         0x06
 #define   ASIC_REV_5780                         0x08
+#define   ASIC_REV_5714                         0x09
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -531,6 +532,8 @@
 #define  MAC_SERDES_CFG_EDGE_SELECT     0x00001000
 #define MAC_SERDES_STAT                        0x00000594
 /* 0x598 --> 0x5b0 unused */
+#define SERDES_RX_CTRL                 0x000005b0      /* 5780/5714 only */
+#define  SERDES_RX_SIG_DETECT           0x00000400
 #define SG_DIG_CTRL                    0x000005b0
 #define  SG_DIG_USING_HW_AUTONEG        0x80000000
 #define  SG_DIG_SOFT_RESET              0x40000000
@@ -1121,7 +1124,14 @@
 /* 0x280 --> 0x400 unused */
 
 #define RX_CPU_BASE                    0x00005000
+#define RX_CPU_MODE                    0x00005000
+#define RX_CPU_STATE                   0x00005004
+#define RX_CPU_PGMCTR                  0x0000501c
+#define RX_CPU_HWBKPT                  0x00005034
 #define TX_CPU_BASE                    0x00005400
+#define TX_CPU_MODE                    0x00005400
+#define TX_CPU_STATE                   0x00005404
+#define TX_CPU_PGMCTR                  0x0000541c
 
 /* Mailboxes */
 #define GRCMBOX_INTERRUPT_0            0x00005800 /* 64-bit */
@@ -1329,6 +1339,8 @@
 #define  GRC_LCLCTRL_CLEARINT          0x00000002
 #define  GRC_LCLCTRL_SETINT            0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN       0x00000008
+#define  GRC_LCLCTRL_USE_SIG_DETECT    0x00000010      /* 5714/5780 only */
+#define  GRC_LCLCTRL_USE_EXT_SIG_DETECT        0x00000020      /* 5714/5780 only */
 #define  GRC_LCLCTRL_GPIO_INPUT3       0x00000020
 #define  GRC_LCLCTRL_GPIO_OE3          0x00000040
 #define  GRC_LCLCTRL_GPIO_OUTPUT3      0x00000080
@@ -1507,6 +1519,7 @@
 #define  FWCMD_NICDRV_IPV6ADDR_CHG      0x00000004
 #define  FWCMD_NICDRV_FIX_DMAR          0x00000005
 #define  FWCMD_NICDRV_FIX_DMAW          0x00000006
+#define  FWCMD_NICDRV_ALIVE2            0x0000000d
 #define NIC_SRAM_FW_CMD_LEN_MBOX       0x00000b7c
 #define NIC_SRAM_FW_CMD_DATA_MBOX      0x00000b80
 #define NIC_SRAM_FW_ASF_STATUS_MBOX    0x00000c00
@@ -1523,6 +1536,12 @@
 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX    0x00000c14
 #define NIC_SRAM_MAC_ADDR_LOW_MBOX     0x00000c18
 
+#define NIC_SRAM_WOL_MBOX              0x00000d30
+#define  WOL_SIGNATURE                  0x474c0000
+#define  WOL_DRV_STATE_SHUTDOWN                 0x00000001
+#define  WOL_DRV_WOL                    0x00000002
+#define  WOL_SET_MAGIC_PKT              0x00000004
+
 #define NIC_SRAM_DATA_CFG_2            0x00000d38
 
 #define  SHASTA_EXT_LED_MODE_MASK       0x00018000
@@ -1559,6 +1578,7 @@
 #define MII_TG3_EXT_CTRL               0x10 /* Extended control register */
 #define  MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
 #define  MII_TG3_EXT_CTRL_LNK3_LED_MODE        0x0002
+#define  MII_TG3_EXT_CTRL_FORCE_LED_OFF        0x0008
 #define  MII_TG3_EXT_CTRL_TBI          0x8000
 
 #define MII_TG3_EXT_STAT               0x11 /* Extended status register */
@@ -2142,6 +2162,8 @@ struct tg3 {
 #define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
 #define TG3_FLAG_10_100_ONLY           0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
+#define TG3_FLAG_IN_RESET_TASK         0x04000000
+#define TG3_FLAG_40BIT_DMA_BUG         0x08000000
 #define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
 #define TG3_FLAG_GOT_SERDES_FLOWCTL    0x20000000
 #define TG3_FLAG_SPLIT_MODE            0x40000000
@@ -2175,6 +2197,7 @@ struct tg3 {
                                        TG3_FLG2_MII_SERDES)
 #define TG3_FLG2_PARALLEL_DETECT       0x01000000
 #define TG3_FLG2_ICH_WORKAROUND                0x02000000
+#define TG3_FLG2_5780_CLASS            0x04000000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3
@@ -2222,6 +2245,7 @@ struct tg3 {
 #define PHY_ID_BCM5705                 0x600081a0
 #define PHY_ID_BCM5750                 0x60008180
 #define PHY_ID_BCM5752                 0x60008100
+#define PHY_ID_BCM5714                 0x60008340
 #define PHY_ID_BCM5780                 0x60008350
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
@@ -2246,13 +2270,14 @@ struct tg3 {
         (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
         (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
         (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
-        (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5780 || \
-        (X) == PHY_ID_BCM8002)
+        (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
+        (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM8002)
 
        struct tg3_hw_stats             *hw_stats;
        dma_addr_t                      stats_mapping;
        struct work_struct              reset_task;
 
+       int                             nvram_lock_cnt;
        u32                             nvram_size;
        u32                             nvram_pagesize;
        u32                             nvram_jedecnum;