myri10ge: update firmware headers

[linux-2.6-omap-h63xx.git] / drivers / net / myri10ge / myri10ge_mcp.h

diff --git a/drivers/net/myri10ge/myri10ge_mcp.h b/drivers/net/myri10ge/myri10ge_mcp.h
index 58e57178c563f6129b4faf80d50e14408a0fe265..fdbeeee073727240a4df96f60b7837f8efc8f0d1 100644 (file)
--- a/drivers/net/myri10ge/myri10ge_mcp.h
+++ b/drivers/net/myri10ge/myri10ge_mcp.h
@@ -10,7 +10,7 @@ struct mcp_dma_addr {
        __be32 low;
 };
 
-/* 4 Bytes.  8 Bytes for NDIS drivers. */
+/* 4 Bytes */
 struct mcp_slot {
        __sum16 checksum;
        __be16 length;
@@ -144,6 +144,7 @@ enum myri10ge_mcp_cmd_type {
         * a power of 2 number of entries.  */
 
        MXGEFW_CMD_SET_INTRQ_SIZE,      /* in bytes */
+#define MXGEFW_CMD_SET_INTRQ_SIZE_FLAG_NO_STRICT_SIZE_CHECK  (1 << 31)
 
        /* command to bring ethernet interface up.  Above parameters
         * (plus mtu & mac address) must have been exchanged prior
@@ -221,10 +222,14 @@ enum myri10ge_mcp_cmd_type {
        MXGEFW_CMD_GET_MAX_RSS_QUEUES,
        MXGEFW_CMD_ENABLE_RSS_QUEUES,
        /* data0 = number of slices n (0, 1, ..., n-1) to enable
-        * data1 = interrupt mode. 0=share one INTx/MSI, 1=use one MSI-X per queue.
+        * data1 = interrupt mode.
+        * 0=share one INTx/MSI, 1=use one MSI-X per queue.
         * If all queues share one interrupt, the driver must have set
         * RSS_SHARED_INTERRUPT_DMA before enabling queues.
         */
+#define MXGEFW_SLICE_INTR_MODE_SHARED 0
+#define MXGEFW_SLICE_INTR_MODE_ONE_PER_SLICE 1
+
        MXGEFW_CMD_GET_RSS_SHARED_INTERRUPT_MASK_OFFSET,
        MXGEFW_CMD_SET_RSS_SHARED_INTERRUPT_DMA,
        /* data0, data1 = bus address lsw, msw */
@@ -241,10 +246,14 @@ enum myri10ge_mcp_cmd_type {
         * 0: disable rss.  nic does not distribute receive packets.
         * 1: enable rss.  nic distributes receive packets among queues.
         * data1 = hash type
-        * 1: IPV4
-        * 2: TCP_IPV4
-        * 3: IPV4 | TCP_IPV4
+        * 1: IPV4            (required by RSS)
+        * 2: TCP_IPV4        (required by RSS)
+        * 3: IPV4 | TCP_IPV4 (required by RSS)
+        * 4: source port
         */
+#define MXGEFW_RSS_HASH_TYPE_IPV4      0x1
+#define MXGEFW_RSS_HASH_TYPE_TCP_IPV4  0x2
+#define MXGEFW_RSS_HASH_TYPE_SRC_PORT  0x4
 
        MXGEFW_CMD_GET_MAX_TSO6_HDR_SIZE,
        /* Return data = the max. size of the entire headers of a IPv6 TSO packet.
@@ -260,6 +269,8 @@ enum myri10ge_mcp_cmd_type {
         * 0: Linux/FreeBSD style (NIC default)
         * 1: NDIS/NetBSD style
         */
+#define MXGEFW_TSO_MODE_LINUX  0
+#define MXGEFW_TSO_MODE_NDIS   1
 
        MXGEFW_CMD_MDIO_READ,
        /* data0 = dev_addr (PMA/PMD or PCS ...), data1 = register/addr */
@@ -286,6 +297,38 @@ enum myri10ge_mcp_cmd_type {
        /* Return data = NIC memory offset of mcp_vpump_public_global */
        MXGEFW_CMD_RESET_VPUMP,
        /* Resets the VPUMP state */
+
+       MXGEFW_CMD_SET_RSS_MCP_SLOT_TYPE,
+       /* data0 = mcp_slot type to use.
+        * 0 = the default 4B mcp_slot
+        * 1 = 8B mcp_slot_8
+        */
+#define MXGEFW_RSS_MCP_SLOT_TYPE_MIN        0
+#define MXGEFW_RSS_MCP_SLOT_TYPE_WITH_HASH  1
+
+       MXGEFW_CMD_SET_THROTTLE_FACTOR,
+       /* set the throttle factor for ethp_z8e
+        * data0 = throttle_factor
+        * throttle_factor = 256 * pcie-raw-speed / tx_speed
+        * tx_speed = 256 * pcie-raw-speed / throttle_factor
+        *
+        * For PCI-E x8: pcie-raw-speed == 16Gb/s
+        * For PCI-E x4: pcie-raw-speed == 8Gb/s
+        *
+        * ex1: throttle_factor == 0x1a0 (416), tx_speed == 1.23GB/s == 9.846 Gb/s
+        * ex2: throttle_factor == 0x200 (512), tx_speed == 1.0GB/s == 8 Gb/s
+        *
+        * with tx_boundary == 2048, max-throttle-factor == 8191 => min-speed == 500Mb/s
+        * with tx_boundary == 4096, max-throttle-factor == 4095 => min-speed == 1Gb/s
+        */
+
+       MXGEFW_CMD_VPUMP_UP,
+       /* Allocates VPump Connection, Send Request and Zero copy buffer address tables */
+       MXGEFW_CMD_GET_VPUMP_CLK,
+       /* Get the lanai clock */
+
+       MXGEFW_CMD_GET_DCA_OFFSET,
+       /* offset of dca control for WDMAs */
 };
 
 enum myri10ge_mcp_cmd_status {
@@ -302,7 +345,8 @@ enum myri10ge_mcp_cmd_status {
        MXGEFW_CMD_ERROR_UNALIGNED,
        MXGEFW_CMD_ERROR_NO_MDIO,
        MXGEFW_CMD_ERROR_XFP_FAILURE,
-       MXGEFW_CMD_ERROR_XFP_ABSENT
+       MXGEFW_CMD_ERROR_XFP_ABSENT,
+       MXGEFW_CMD_ERROR_BAD_PCIE_LINK
 };
 
 #define MXGEFW_OLD_IRQ_DATA_LEN 40