ARM: OMAP: Remove io_p2v, use ioremap and XXX_IO_ADDRESS

[linux-2.6-omap-h63xx.git] / drivers / mtd / nand / omap-hw.c

diff --git a/drivers/mtd/nand/omap-hw.c b/drivers/mtd/nand/omap-hw.c
index d0e7e829e7144e725ae8f12210aa1ef7306d59ae..1eb19ce0a0b6bad744111a8d9a475db5801efc40 100644 (file)
--- a/drivers/mtd/nand/omap-hw.c
+++ b/drivers/mtd/nand/omap-hw.c
@@ -43,8 +43,8 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/dma.h>
+#include <mach/board.h>
+#include <mach/dma.h>
 
 #define NAND_BASE              0xfffbcc00
 #define NND_REVISION           0x00
@@ -165,7 +165,7 @@ static struct mtd_info *omap_mtd;
 static struct clk *omap_nand_clk;
 static int omap_nand_dma_ch;
 static struct completion omap_nand_dma_comp;
-static unsigned long omap_nand_base = io_p2v(NAND_BASE);
+static unsigned long omap_nand_base = OMAP1_IO_ADDRESS(NAND_BASE);
 
 static inline u32 nand_read_reg(int idx)
 {
@@ -256,7 +256,7 @@ static void omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
        init_completion(&omap_nand_dma_comp);
 
        len = u32_count << 2;
-       consistent_sync(addr, len, DMA_TO_DEVICE);
+       dma_cache_maint(addr, len, DMA_TO_DEVICE);
        omap_start_dma(dma_ch);
        jiffies_before = jiffies;
        timeout = wait_for_completion_timeout(&omap_nand_dma_comp,
@@ -269,17 +269,9 @@ static void omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
                printk(KERN_WARNING "omap-hw-nand: DMA timeout after %u ms, max. seen latency %u ms\n",
                       jiffies_to_msecs(jiffies_spent),
                       jiffies_to_msecs(max_jiffies));
-               if (OMAP_DMA_CCR_REG(dma_ch) & (1 << 7)) {
-                       /* If the DMA transfer is still running, something
-                        * is really wrong. */
-                       printk(KERN_ERR "omap-hw-nand: DMA transfer still running. Not good.\n");
-                       printk(KERN_INFO "DMA ch %d: CCR %04x, CSR %04x, CCDEN_L %04x\n",
-                              dma_ch, omap_readw(OMAP_DMA_CCR_REG(dma_ch)), omap_readw(OMAP_DMA_CSR_REG(dma_ch)),
-                              omap_readw(OMAP_DMA_BASE + 0x40 * (dma_ch) + 0x34));
-               }
        }
        if (!is_write)
-               consistent_sync(addr, len, DMA_FROM_DEVICE);
+               dma_cache_maint(addr, len, DMA_FROM_DEVICE);
 
        nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) & ~((1 << 16) | (1 << 17)));
 }
@@ -386,11 +378,6 @@ static u_char omap_nand_read_byte(struct mtd_info *mtd)
        return nand_read_reg8(NND_ACCESS);
 }
 
-static void omap_nand_write_byte(struct mtd_info *mtd, u_char byte)
-{
-       nand_write_reg8(NND_ACCESS, byte);
-}
-
 static int omap_nand_dev_ready(struct mtd_info *mtd)
 {
        u32 l;
@@ -425,9 +412,9 @@ static void omap_nand_command(struct mtd_info *mtd, unsigned command, int column
        if (command == NAND_CMD_SEQIN) {
                int readcmd;
 
-               if (column >= mtd->oobblock) {
+               if (column >= mtd->writesize) {
                        /* OOB area */
-                       column -= mtd->oobblock;
+                       column -= mtd->writesize;
                        readcmd = NAND_CMD_READOOB;
                } else if (column < 256) {
                        /* First 256 bytes --> READ0 */
@@ -458,7 +445,7 @@ static void omap_nand_command_lp(struct mtd_info *mtd, unsigned command, int col
        struct nand_chip *this = mtd->priv;
 
        if (command == NAND_CMD_READOOB) {
-               column += mtd->oobblock;
+               column += mtd->writesize;
                command = NAND_CMD_READ0;
        }
        switch (command) {
@@ -495,7 +482,8 @@ static int omap_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_ch
        int n;
        struct nand_chip *this = mtd->priv;
 
-       if (this->eccmode == NAND_ECC_HW12_2048)
+       /* Ex NAND_ECC_HW12_2048 */
+       if ((this->ecc.mode == NAND_ECC_HW) && (this->ecc.size  == 2048))
                n = 4;
        else
                n = 1;
@@ -642,7 +630,8 @@ static int omap_nand_correct_data(struct mtd_info *mtd, u_char *dat, u_char *rea
        int block_count = 0, i, r;
 
        this = mtd->priv;
-       if (this->eccmode == NAND_ECC_HW12_2048)
+       /* Ex NAND_ECC_HW12_2048 */
+       if ((this->ecc.mode == NAND_ECC_HW) && (this->ecc.size  == 2048))
                block_count = 4;
        else
                block_count = 1;
@@ -672,12 +661,12 @@ static int __init add_dynamic_parts(struct mtd_info *mtd)
 {
        static const char *part_parsers[] = { "cmdlinepart", NULL };
        struct mtd_partition *parts;
-       const struct omap_flash_part_config *cfg;
+       const struct omap_flash_part_str_config *cfg;
        char *part_str = NULL;
        size_t part_str_len;
        int c;
 
-       cfg = omap_get_var_config(OMAP_TAG_FLASH_PART, &part_str_len);
+       cfg = omap_get_var_config(OMAP_TAG_FLASH_PART_STR, &part_str_len);
        if (cfg != NULL) {
                part_str = kmalloc(part_str_len + 1, GFP_KERNEL);
                if (part_str == NULL)
@@ -794,19 +783,20 @@ static int __init omap_nand_init(void)
 
        /* Used from chip select and nand_command() */
        this->read_byte = omap_nand_read_byte;
-       this->write_byte = omap_nand_write_byte;
-
-       this->select_chip = omap_nand_select_chip;
-       this->dev_ready = omap_nand_dev_ready;
-       this->chip_delay = 0;
-       this->eccmode = NAND_ECC_HW3_512; 
-       this->cmdfunc = omap_nand_command;
-       this->write_buf = omap_nand_write_buf;
-       this->read_buf = omap_nand_read_buf;
-       this->verify_buf = omap_nand_verify_buf;
-       this->calculate_ecc = omap_nand_calculate_ecc;
-       this->correct_data = omap_nand_correct_data;
-       this->enable_hwecc = omap_nand_enable_hwecc;
+
+       this->select_chip   = omap_nand_select_chip;
+       this->dev_ready     = omap_nand_dev_ready;
+       this->chip_delay    = 0;
+       this->ecc.mode      = NAND_ECC_HW;
+       this->ecc.bytes     = 3;
+       this->ecc.size      = 512;
+       this->cmdfunc       = omap_nand_command;
+       this->write_buf     = omap_nand_write_buf;
+       this->read_buf      = omap_nand_read_buf;
+       this->verify_buf    = omap_nand_verify_buf;
+       this->ecc.calculate = omap_nand_calculate_ecc;
+       this->ecc.correct   = omap_nand_correct_data;
+       this->ecc.hwctl     = omap_nand_enable_hwecc;
 
        nand_write_reg(NND_SYSCFG, 0x1); /* Enable auto idle */
        nand_write_reg(NND_PSC_CLK, 10);
@@ -822,11 +812,10 @@ static int __init omap_nand_init(void)
                l = nand_read_reg(NND_CTRL);
                l |= 1 << 4; /* Set the A8 bit in CTRL reg */
                nand_write_reg(NND_CTRL, l);
-               this->eccmode = NAND_ECC_HW12_2048;
-               this->eccsteps = 1;
-               this->eccsize = 2048;
-               this->eccbytes = 12;
-               omap_mtd->eccsize = 2048;
+               this->ecc.mode = NAND_ECC_HW;
+               this->ecc.steps = 1;
+               this->ecc.size = 2048;
+               this->ecc.bytes = 12;
                nand_write_reg(NND_ECC_SELECT, 6);
        }