#include <asm/io.h>
-#include <asm/arch/board.h>
-#include <asm/arch/dma.h>
+#include <mach/board.h>
+#include <mach/dma.h>
#define NAND_BASE 0xfffbcc00
#define NND_REVISION 0x00
static struct clk *omap_nand_clk;
static int omap_nand_dma_ch;
static struct completion omap_nand_dma_comp;
-static unsigned long omap_nand_base = io_p2v(NAND_BASE);
+static unsigned long omap_nand_base = OMAP1_IO_ADDRESS(NAND_BASE);
static inline u32 nand_read_reg(int idx)
{
init_completion(&omap_nand_dma_comp);
len = u32_count << 2;
- consistent_sync(addr, len, DMA_TO_DEVICE);
+ dma_cache_maint(addr, len, DMA_TO_DEVICE);
omap_start_dma(dma_ch);
jiffies_before = jiffies;
timeout = wait_for_completion_timeout(&omap_nand_dma_comp,
printk(KERN_WARNING "omap-hw-nand: DMA timeout after %u ms, max. seen latency %u ms\n",
jiffies_to_msecs(jiffies_spent),
jiffies_to_msecs(max_jiffies));
- if (OMAP_DMA_CCR_REG(dma_ch) & (1 << 7)) {
- /* If the DMA transfer is still running, something
- * is really wrong. */
- printk(KERN_ERR "omap-hw-nand: DMA transfer still running. Not good.\n");
- printk(KERN_INFO "DMA ch %d: CCR %04x, CSR %04x, CCDEN_L %04x\n",
- dma_ch, omap_readw(OMAP_DMA_CCR_REG(dma_ch)), omap_readw(OMAP_DMA_CSR_REG(dma_ch)),
- omap_readw(OMAP_DMA_BASE + 0x40 * (dma_ch) + 0x34));
- }
}
if (!is_write)
- consistent_sync(addr, len, DMA_FROM_DEVICE);
+ dma_cache_maint(addr, len, DMA_FROM_DEVICE);
nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) & ~((1 << 16) | (1 << 17)));
}
this->ecc.steps = 1;
this->ecc.size = 2048;
this->ecc.bytes = 12;
- omap_mtd->eccsize = 2048;
nand_write_reg(NND_ECC_SELECT, 6);
}