ARM: OMAP: Remove io_p2v, use ioremap and XXX_IO_ADDRESS

[linux-2.6-omap-h63xx.git] / drivers / mtd / nand / omap-hw.c

diff --git a/drivers/mtd/nand/omap-hw.c b/drivers/mtd/nand/omap-hw.c
index 330a9dca272e8743751b1296fd55529be985ab92..1eb19ce0a0b6bad744111a8d9a475db5801efc40 100644 (file)
--- a/drivers/mtd/nand/omap-hw.c
+++ b/drivers/mtd/nand/omap-hw.c
@@ -43,8 +43,8 @@
 
 #include <asm/io.h>
 
-#include <asm/arch/board.h>
-#include <asm/arch/dma.h>
+#include <mach/board.h>
+#include <mach/dma.h>
 
 #define NAND_BASE              0xfffbcc00
 #define NND_REVISION           0x00
@@ -165,7 +165,7 @@ static struct mtd_info *omap_mtd;
 static struct clk *omap_nand_clk;
 static int omap_nand_dma_ch;
 static struct completion omap_nand_dma_comp;
-static unsigned long omap_nand_base = io_p2v(NAND_BASE);
+static unsigned long omap_nand_base = OMAP1_IO_ADDRESS(NAND_BASE);
 
 static inline u32 nand_read_reg(int idx)
 {
@@ -256,7 +256,7 @@ static void omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
        init_completion(&omap_nand_dma_comp);
 
        len = u32_count << 2;
-       consistent_sync(addr, len, DMA_TO_DEVICE);
+       dma_cache_maint(addr, len, DMA_TO_DEVICE);
        omap_start_dma(dma_ch);
        jiffies_before = jiffies;
        timeout = wait_for_completion_timeout(&omap_nand_dma_comp,
@@ -269,17 +269,9 @@ static void omap_nand_dma_transfer(struct mtd_info *mtd, void *addr,
                printk(KERN_WARNING "omap-hw-nand: DMA timeout after %u ms, max. seen latency %u ms\n",
                       jiffies_to_msecs(jiffies_spent),
                       jiffies_to_msecs(max_jiffies));
-               if (OMAP_DMA_CCR_REG(dma_ch) & (1 << 7)) {
-                       /* If the DMA transfer is still running, something
-                        * is really wrong. */
-                       printk(KERN_ERR "omap-hw-nand: DMA transfer still running. Not good.\n");
-                       printk(KERN_INFO "DMA ch %d: CCR %04x, CSR %04x, CCDEN_L %04x\n",
-                              dma_ch, omap_readw(OMAP_DMA_CCR_REG(dma_ch)), omap_readw(OMAP_DMA_CSR_REG(dma_ch)),
-                              omap_readw(OMAP_DMA_BASE + 0x40 * (dma_ch) + 0x34));
-               }
        }
        if (!is_write)
-               consistent_sync(addr, len, DMA_FROM_DEVICE);
+               dma_cache_maint(addr, len, DMA_FROM_DEVICE);
 
        nand_write_reg(NND_CTRL, nand_read_reg(NND_CTRL) & ~((1 << 16) | (1 << 17)));
 }