#include <linux/sm501.h>
#include <linux/sm501-regs.h>
+#include <linux/serial_8250.h>
#include <asm/io.h>
unsigned int pdev_id;
unsigned int irq;
void __iomem *regs;
+ unsigned int rev;
};
#define MHZ (1000 * 1000)
#ifdef DEBUG
-static const unsigned int misc_div[] = {
- [0] = 1,
- [1] = 2,
- [2] = 4,
- [3] = 8,
- [4] = 16,
- [5] = 32,
- [6] = 64,
- [7] = 128,
- [8] = 3,
- [9] = 6,
- [10] = 12,
- [11] = 24,
- [12] = 48,
- [13] = 96,
- [14] = 192,
- [15] = 384,
-};
-
-static const unsigned int px_div[] = {
+static const unsigned int div_tab[] = {
[0] = 1,
[1] = 2,
[2] = 4,
static unsigned long decode_div(unsigned long pll2, unsigned long val,
unsigned int lshft, unsigned int selbit,
- unsigned long mask, const unsigned int *dtab)
+ unsigned long mask)
{
if (val & selbit)
pll2 = 288 * MHZ;
- return pll2 / dtab[(val >> lshft) & mask];
+ return pll2 / div_tab[(val >> lshft) & mask];
}
#define fmt_freq(x) ((x) / MHZ), ((x) % MHZ), (x)
}
sdclk0 = (misct & (1<<12)) ? pll2 : 288 * MHZ;
- sdclk0 /= misc_div[((misct >> 8) & 0xf)];
+ sdclk0 /= div_tab[((misct >> 8) & 0xf)];
sdclk1 = (misct & (1<<20)) ? pll2 : 288 * MHZ;
- sdclk1 /= misc_div[((misct >> 16) & 0xf)];
+ sdclk1 /= div_tab[((misct >> 16) & 0xf)];
dev_dbg(sm->dev, "MISCT=%08lx, PM0=%08lx, PM1=%08lx\n",
misct, pm0, pm1);
"P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
"M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
(pmc & 3 ) == 0 ? '*' : '-',
- fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31, px_div)),
- fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15, misc_div)),
- fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15, misc_div)),
- fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15, misc_div)));
+ fmt_freq(decode_div(pll2, pm0, 24, 1<<29, 31)),
+ fmt_freq(decode_div(pll2, pm0, 16, 1<<20, 15)),
+ fmt_freq(decode_div(pll2, pm0, 8, 1<<12, 15)),
+ fmt_freq(decode_div(pll2, pm0, 0, 1<<4, 15)));
dev_dbg(sm->dev, "PM1[%c]: "
"P2 %ld.%ld MHz (%ld), V2 %ld.%ld (%ld), "
"M %ld.%ld (%ld), MX1 %ld.%ld (%ld)\n",
(pmc & 3 ) == 1 ? '*' : '-',
- fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31, px_div)),
- fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15, misc_div)),
- fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15, misc_div)),
- fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15, misc_div)));
+ fmt_freq(decode_div(pll2, pm1, 24, 1<<29, 31)),
+ fmt_freq(decode_div(pll2, pm1, 16, 1<<20, 15)),
+ fmt_freq(decode_div(pll2, pm1, 8, 1<<12, 15)),
+ fmt_freq(decode_div(pll2, pm1, 0, 1<<4, 15)));
}
static void sm501_dump_regs(struct sm501_devdata *sm)
mode &= 3; /* get current power mode */
if (unit >= ARRAY_SIZE(sm->unit_power)) {
- dev_err(dev, "%s: bad unit %d\n", __FUNCTION__, unit);
+ dev_err(dev, "%s: bad unit %d\n", __func__, unit);
goto already;
}
- dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __FUNCTION__, unit,
+ dev_dbg(sm->dev, "%s: unit %d, cur %d, to %d\n", __func__, unit,
sm->unit_power[unit], to);
if (to == 0 && sm->unit_power[unit] == 0) {
unsigned long mclk;
int divider;
int shift;
+ unsigned int m, n, k;
};
+/* sm501_calc_clock
+ *
+ * Calculates the nearest discrete clock frequency that
+ * can be achieved with the specified input clock.
+ * the maximum divisor is 3 or 5
+ */
+
+static int sm501_calc_clock(unsigned long freq,
+ struct sm501_clock *clock,
+ int max_div,
+ unsigned long mclk,
+ long *best_diff)
+{
+ int ret = 0;
+ int divider;
+ int shift;
+ long diff;
+
+ /* try dividers 1 and 3 for CRT and for panel,
+ try divider 5 for panel only.*/
+
+ for (divider = 1; divider <= max_div; divider += 2) {
+ /* try all 8 shift values.*/
+ for (shift = 0; shift < 8; shift++) {
+ /* Calculate difference to requested clock */
+ diff = sm501fb_round_div(mclk, divider << shift) - freq;
+ if (diff < 0)
+ diff = -diff;
+
+ /* If it is less than the current, use it */
+ if (diff < *best_diff) {
+ *best_diff = diff;
+
+ clock->mclk = mclk;
+ clock->divider = divider;
+ clock->shift = shift;
+ ret = 1;
+ }
+ }
+ }
+
+ return ret;
+}
+
+/* sm501_calc_pll
+ *
+ * Calculates the nearest discrete clock frequency that can be
+ * achieved using the programmable PLL.
+ * the maximum divisor is 3 or 5
+ */
+
+static unsigned long sm501_calc_pll(unsigned long freq,
+ struct sm501_clock *clock,
+ int max_div)
+{
+ unsigned long mclk;
+ unsigned int m, n, k;
+ long best_diff = 999999999;
+
+ /*
+ * The SM502 datasheet doesn't specify the min/max values for M and N.
+ * N = 1 at least doesn't work in practice.
+ */
+ for (m = 2; m <= 255; m++) {
+ for (n = 2; n <= 127; n++) {
+ for (k = 0; k <= 1; k++) {
+ mclk = (24000000UL * m / n) >> k;
+
+ if (sm501_calc_clock(freq, clock, max_div,
+ mclk, &best_diff)) {
+ clock->m = m;
+ clock->n = n;
+ clock->k = k;
+ }
+ }
+ }
+ }
+
+ /* Return best clock. */
+ return clock->mclk / (clock->divider << clock->shift);
+}
+
/* sm501_select_clock
*
- * selects nearest discrete clock frequency the SM501 can achive
+ * Calculates the nearest discrete clock frequency that can be
+ * achieved using the 288MHz and 336MHz PLLs.
* the maximum divisor is 3 or 5
*/
+
static unsigned long sm501_select_clock(unsigned long freq,
struct sm501_clock *clock,
int max_div)
{
unsigned long mclk;
- int divider;
- int shift;
- long diff;
long best_diff = 999999999;
/* Try 288MHz and 336MHz clocks. */
for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) {
- /* try dividers 1 and 3 for CRT and for panel,
- try divider 5 for panel only.*/
-
- for (divider = 1; divider <= max_div; divider += 2) {
- /* try all 8 shift values.*/
- for (shift = 0; shift < 8; shift++) {
- /* Calculate difference to requested clock */
- diff = sm501fb_round_div(mclk, divider << shift) - freq;
- if (diff < 0)
- diff = -diff;
-
- /* If it is less than the current, use it */
- if (diff < best_diff) {
- best_diff = diff;
-
- clock->mclk = mclk;
- clock->divider = divider;
- clock->shift = shift;
- }
- }
- }
+ sm501_calc_clock(freq, clock, max_div, mclk, &best_diff);
}
/* Return best clock. */
unsigned long gate = readl(sm->regs + SM501_CURRENT_GATE);
unsigned long clock = readl(sm->regs + SM501_CURRENT_CLOCK);
unsigned char reg;
+ unsigned int pll_reg = 0;
unsigned long sm501_freq; /* the actual frequency acheived */
struct sm501_clock to;
* requested frequency the value must be multiplied by
* 2. This clock also has an additional pre divisor */
- sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
- reg=to.shift & 0x07;/* bottom 3 bits are shift */
- if (to.divider == 3)
- reg |= 0x08; /* /3 divider required */
- else if (to.divider == 5)
- reg |= 0x10; /* /5 divider required */
- if (to.mclk != 288000000)
- reg |= 0x20; /* which mclk pll is source */
+ if (sm->rev >= 0xC0) {
+ /* SM502 -> use the programmable PLL */
+ sm501_freq = (sm501_calc_pll(2 * req_freq,
+ &to, 5) / 2);
+ reg = to.shift & 0x07;/* bottom 3 bits are shift */
+ if (to.divider == 3)
+ reg |= 0x08; /* /3 divider required */
+ else if (to.divider == 5)
+ reg |= 0x10; /* /5 divider required */
+ reg |= 0x40; /* select the programmable PLL */
+ pll_reg = 0x20000 | (to.k << 15) | (to.n << 8) | to.m;
+ } else {
+ sm501_freq = (sm501_select_clock(2 * req_freq,
+ &to, 5) / 2);
+ reg = to.shift & 0x07;/* bottom 3 bits are shift */
+ if (to.divider == 3)
+ reg |= 0x08; /* /3 divider required */
+ else if (to.divider == 5)
+ reg |= 0x10; /* /5 divider required */
+ if (to.mclk != 288000000)
+ reg |= 0x20; /* which mclk pll is source */
+ }
break;
case SM501_CLOCK_V2XCLK:
}
writel(mode, sm->regs + SM501_POWER_MODE_CONTROL);
+
+ if (pll_reg)
+ writel(pll_reg, sm->regs + SM501_PROGRAMMABLE_PLL_CONTROL);
+
sm501_sync_regs(sm);
dev_info(sm->dev, "gate %08lx, clock %08lx, mode %08lx\n",
* finds the closest available frequency for a given clock
*/
-unsigned long sm501_find_clock(int clksrc,
+unsigned long sm501_find_clock(struct device *dev,
+ int clksrc,
unsigned long req_freq)
{
+ struct sm501_devdata *sm = dev_get_drvdata(dev);
unsigned long sm501_freq; /* the frequency achiveable by the 501 */
struct sm501_clock to;
switch (clksrc) {
case SM501_CLOCK_P2XCLK:
- sm501_freq = (sm501_select_clock(2 * req_freq, &to, 5) / 2);
+ if (sm->rev >= 0xC0) {
+ /* SM502 -> use the programmable PLL */
+ sm501_freq = (sm501_calc_pll(2 * req_freq,
+ &to, 5) / 2);
+ } else {
+ sm501_freq = (sm501_select_clock(2 * req_freq,
+ &to, 5) / 2);
+ }
break;
case SM501_CLOCK_V2XCLK:
*/
static struct platform_device *
-sm501_create_subdev(struct sm501_devdata *sm,
- char *name, unsigned int res_count)
+sm501_create_subdev(struct sm501_devdata *sm, char *name,
+ unsigned int res_count, unsigned int platform_data_size)
{
struct sm501_device *smdev;
smdev = kzalloc(sizeof(struct sm501_device) +
- sizeof(struct resource) * res_count, GFP_KERNEL);
+ (sizeof(struct resource) * res_count) +
+ platform_data_size, GFP_KERNEL);
if (!smdev)
return NULL;
smdev->pdev.name = name;
smdev->pdev.id = sm->pdev_id;
- smdev->pdev.resource = (struct resource *)(smdev+1);
- smdev->pdev.num_resources = res_count;
-
smdev->pdev.dev.parent = sm->dev;
+ if (res_count) {
+ smdev->pdev.resource = (struct resource *)(smdev+1);
+ smdev->pdev.num_resources = res_count;
+ }
+ if (platform_data_size)
+ smdev->pdev.dev.platform_data = (void *)(smdev+1);
+
return &smdev->pdev;
}
{
struct platform_device *pdev;
- pdev = sm501_create_subdev(sm, "sm501-usb", 3);
+ pdev = sm501_create_subdev(sm, "sm501-usb", 3, 0);
if (!pdev)
return -ENOMEM;
return sm501_register_device(sm, pdev);
}
+static void sm501_setup_uart_data(struct sm501_devdata *sm,
+ struct plat_serial8250_port *uart_data,
+ unsigned int offset)
+{
+ uart_data->membase = sm->regs + offset;
+ uart_data->mapbase = sm->io_res->start + offset;
+ uart_data->iotype = UPIO_MEM;
+ uart_data->irq = sm->irq;
+ uart_data->flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_SHARE_IRQ;
+ uart_data->regshift = 2;
+ uart_data->uartclk = (9600 * 16);
+}
+
+static int sm501_register_uart(struct sm501_devdata *sm, int devices)
+{
+ struct platform_device *pdev;
+ struct plat_serial8250_port *uart_data;
+
+ pdev = sm501_create_subdev(sm, "serial8250", 0,
+ sizeof(struct plat_serial8250_port) * 3);
+ if (!pdev)
+ return -ENOMEM;
+
+ uart_data = pdev->dev.platform_data;
+
+ if (devices & SM501_USE_UART0) {
+ sm501_setup_uart_data(sm, uart_data++, 0x30000);
+ sm501_unit_power(sm->dev, SM501_GATE_UART0, 1);
+ sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 12, 0);
+ sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x01e0, 0);
+ }
+ if (devices & SM501_USE_UART1) {
+ sm501_setup_uart_data(sm, uart_data++, 0x30020);
+ sm501_unit_power(sm->dev, SM501_GATE_UART1, 1);
+ sm501_modify_reg(sm->dev, SM501_IRQ_MASK, 1 << 13, 0);
+ sm501_modify_reg(sm->dev, SM501_GPIO63_32_CONTROL, 0x1e00, 0);
+ }
+
+ pdev->id = PLAT8250_DEV_SM501;
+
+ return sm501_register_device(sm, pdev);
+}
+
static int sm501_register_display(struct sm501_devdata *sm,
resource_size_t *mem_avail)
{
struct platform_device *pdev;
- pdev = sm501_create_subdev(sm, "sm501-fb", 4);
+ pdev = sm501_create_subdev(sm, "sm501-fb", 4, 0);
if (!pdev)
return -ENOMEM;
static int sm501_init_dev(struct sm501_devdata *sm)
{
+ struct sm501_initdata *idata;
resource_size_t mem_avail;
unsigned long dramctrl;
unsigned long devid;
return -EINVAL;
}
+ /* disable irqs */
+ writel(0, sm->regs + SM501_IRQ_MASK);
+
dramctrl = readl(sm->regs + SM501_DRAM_CONTROL);
mem_avail = sm501_mem_local[(dramctrl >> 13) & 0x7];
dev_info(sm->dev, "SM501 At %p: Version %08lx, %ld Mb, IRQ %d\n",
sm->regs, devid, (unsigned long)mem_avail >> 20, sm->irq);
+ sm->rev = devid & SM501_DEVICEID_REVMASK;
+
sm501_dump_gate(sm);
ret = device_create_file(sm->dev, &dev_attr_dbg_regs);
/* check to see if we have some device initialisation */
- if (sm->platdata) {
- struct sm501_platdata *pdata = sm->platdata;
-
- if (pdata->init) {
- sm501_init_regs(sm, sm->platdata->init);
+ idata = sm->platdata ? sm->platdata->init : NULL;
+ if (idata) {
+ sm501_init_regs(sm, idata);
- if (pdata->init->devices & SM501_USE_USB_HOST)
- sm501_register_usbhost(sm, &mem_avail);
- }
+ if (idata->devices & SM501_USE_USB_HOST)
+ sm501_register_usbhost(sm, &mem_avail);
+ if (idata->devices & (SM501_USE_UART0 | SM501_USE_UART1))
+ sm501_register_uart(sm, idata->devices);
}
ret = sm501_check_clocks(sm);
.remove = sm501_pci_remove,
};
+MODULE_ALIAS("platform:sm501");
+
static struct platform_driver sm501_plat_drv = {
.driver = {
.name = "sm501",
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