ide: make void and rename ide_dma_lostirq() method

[linux-2.6-omap-h63xx.git] / drivers / ide / pci / hpt366.c

diff --git a/drivers/ide/pci/hpt366.c b/drivers/ide/pci/hpt366.c
index fcbc5605b38ef28210d11bdf7f33051bad56312d..34d06dc7f2b2d2c43bb25c674d4b3af16eb971b6 100644 (file)
--- a/drivers/ide/pci/hpt366.c
+++ b/drivers/ide/pci/hpt366.c
@@ -1,5 +1,5 @@
 /*
- * linux/drivers/ide/pci/hpt366.c              Version 1.03    May 4, 2007
+ * linux/drivers/ide/pci/hpt366.c              Version 1.06    Jun 27, 2007
  *
  * Copyright (C) 1999-2003             Andre Hedrick <andre@linux-ide.org>
  * Portions Copyright (C) 2001         Sun Microsystems, Inc.
@@ -106,7 +106,8 @@
  *   switch  to calculating  PCI clock frequency based on the chip's base DPLL
  *   frequency
  * - switch to using the  DPLL clock and enable UltraATA/133 mode by default on
- *   anything  newer than HPT370/A
+ *   anything  newer than HPT370/A (except HPT374 that is not capable of this
+ *   mode according to the manual)
  * - fold PCI clock detection and DPLL setup code into init_chipset_hpt366(),
  *   also fixing the interchanged 25/40 MHz PCI clock cases for HPT36x chips;
  *   unify HPT36x/37x timing setup code and the speedproc handlers by joining
@@ -181,6 +182,7 @@ static const char *bad_ata66_4[] = {
        "IC35L040AVER07-0",
        "IC35L060AVER07-0",
        "WDC AC310200R",
+       "MAXTOR STM3320620A",
        NULL
 };
 
@@ -365,7 +367,6 @@ static u32 sixty_six_base_hpt37x[] = {
 };
 
 #define HPT366_DEBUG_DRIVE_INFO                0
-#define HPT374_ALLOW_ATA133_6          1
 #define HPT371_ALLOW_ATA133_6          1
 #define HPT302_ALLOW_ATA133_6          1
 #define HPT372_ALLOW_ATA133_6          1
@@ -450,7 +451,7 @@ static struct hpt_info hpt370a __devinitdata = {
 
 static struct hpt_info hpt374 __devinitdata = {
        .chip_type      = HPT374,
-       .max_mode       = HPT374_ALLOW_ATA133_6 ? 4 : 3,
+       .max_mode       = 3,
        .dpll_clk       = 48,
        .settings       = hpt37x_settings
 };
@@ -736,7 +737,7 @@ static int hpt366_config_drive_xfer_rate(ide_drive_t *drive)
  * This is specific to the HPT366 UDMA chipset
  * by HighPoint|Triones Technologies, Inc.
  */
-static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
+static void hpt366_dma_lost_irq(ide_drive_t *drive)
 {
        struct pci_dev *dev = HWIF(drive)->pci_dev;
        u8 mcr1 = 0, mcr3 = 0, scr1 = 0;
@@ -748,7 +749,7 @@ static int hpt366_ide_dma_lostirq(ide_drive_t *drive)
                drive->name, __FUNCTION__, mcr1, mcr3, scr1);
        if (scr1 & 0x10)
                pci_write_config_byte(dev, 0x5a, scr1 & ~0x10);
-       return __ide_dma_lostirq(drive);
+       ide_dma_lost_irq(drive);
 }
 
 static void hpt370_clear_engine(ide_drive_t *drive)
@@ -1354,7 +1355,7 @@ static void __devinit init_hwif_hpt366(ide_hwif_t *hwif)
                hwif->ide_dma_end       = &hpt370_ide_dma_end;
                hwif->ide_dma_timeout   = &hpt370_ide_dma_timeout;
        } else
-               hwif->ide_dma_lostirq   = &hpt366_ide_dma_lostirq;
+               hwif->dma_lost_irq      = &hpt366_dma_lost_irq;
 
        if (!noautodma)
                hwif->autodma = 1;
@@ -1513,18 +1514,28 @@ static int __devinit init_setup_hpt366(struct pci_dev *dev, ide_pci_device_t *d)
                goto init_single;
 
        /*
-        * HPT36x chips are single channel and
-        * do not seem to have the channel enable bit...
+        * HPT36x chips have one channel per function and have
+        * both channel enable bits located differently and visible
+        * to both functions -- really stupid design decision... :-(
+        * Bit 4 is for the primary channel, bit 5 for the secondary.
         */
        d->channels = 1;
-       d->enablebits[0].reg = 0;
+       d->enablebits[0].mask = d->enablebits[0].val = 0x10;
 
        if ((dev2 = pci_get_slot(dev->bus, dev->devfn + 1)) != NULL) {
-               u8  pin1 = 0, pin2 = 0;
+               u8  mcr1 = 0, pin1 = 0, pin2 = 0;
                int ret;
 
                pci_set_drvdata(dev2, info[rev]);
 
+               /*
+                * Now we'll have to force both channels enabled if
+                * at least one of them has been enabled by BIOS...
+                */
+               pci_read_config_byte(dev, 0x50, &mcr1);
+               if (mcr1 & 0x30)
+                       pci_write_config_byte(dev, 0x50, mcr1 | 0x30);
+
                pci_read_config_byte(dev,  PCI_INTERRUPT_PIN, &pin1);
                pci_read_config_byte(dev2, PCI_INTERRUPT_PIN, &pin2);
                if (pin1 != pin2 && dev->irq == dev2->irq) {