Merge git://git.infradead.org/mtd-2.6

[linux-2.6-omap-h63xx.git] / drivers / gpu / drm / radeon / radeon_cp.c

diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index 248ab4a7d39fdb42a1073f48cceca3ed237d28ce..073894824e6b0f530a18fe4a37b233faba16d400 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -71,7 +71,8 @@ static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 
 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 {
-       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+       if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                return RS690_READ_MCIND(dev_priv, addr);
        else
                return RS480_READ_MCIND(dev_priv, addr);
@@ -82,7 +83,8 @@ u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
                return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
-       else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+       else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
                return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
@@ -94,7 +96,8 @@ static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 {
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
                R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
-       else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+       else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
                R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
@@ -106,7 +109,8 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
 {
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
                R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
-       else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+       else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
        else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
                R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
@@ -122,15 +126,17 @@ static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
        if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
                R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
                R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
-       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
                RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
                RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
        } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
                R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
                R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
-       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
                RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
-               RADEON_WRITE(RS480_AGP_BASE_2, 0);
+               RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
        } else {
                RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
                if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
@@ -347,6 +353,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
                DRM_INFO("Loading R300 Microcode\n");
                for (i = 0; i < 256; i++) {
@@ -356,6 +363,7 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                                     R300_cp_microcode[i][0]);
                }
        } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
                DRM_INFO("Loading R400 Microcode\n");
                for (i = 0; i < 256; i++) {
@@ -364,8 +372,9 @@ static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
                                     R420_cp_microcode[i][0]);
                }
-       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
-               DRM_INFO("Loading RS690 Microcode\n");
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
+               DRM_INFO("Loading RS690/RS740 Microcode\n");
                for (i = 0; i < 256; i++) {
                        RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
                                     RS690_cp_microcode[i][1]);
@@ -626,8 +635,6 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
                     dev_priv->ring.size_l2qw);
 #endif
 
-       /* Start with assuming that writeback doesn't work */
-       dev_priv->writeback_works = 0;
 
        /* Initialize the scratch register pointer.  This will cause
         * the scratch register values to be written out to memory
@@ -646,8 +653,19 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
        RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 
        /* Turn on bus mastering */
-       tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
-       RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+       if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
+               /* rs600/rs690/rs740 */
+               tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
+               RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+       } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
+                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
+               /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
+               tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
+               RADEON_WRITE(RADEON_BUS_CNTL, tmp);
+       } /* PCIE cards appears to not need this */
 
        dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
        RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
@@ -674,6 +692,9 @@ static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 {
        u32 tmp;
 
+       /* Start with assuming that writeback doesn't work */
+       dev_priv->writeback_works = 0;
+
        /* Writeback doesn't seem to work everywhere, test it here and possibly
         * enable it if it appears to work
         */
@@ -719,7 +740,8 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
                          dev_priv->gart_size);
 
                temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
-               if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690)
+               if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
                        IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
                                                             RS690_BLOCK_GFX_D3_EN));
                else
@@ -812,6 +834,7 @@ static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
        u32 tmp;
 
        if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
+           ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
            (dev_priv->flags & RADEON_IS_IGPGART)) {
                radeon_set_igpgart(dev_priv, on);
                return;
@@ -1286,7 +1309,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
        radeon_cp_init_ring_buffer(dev, dev_priv);
 
        radeon_do_engine_reset(dev);
-       radeon_enable_interrupt(dev);
+       radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
 
        DRM_DEBUG("radeon_do_resume_cp() complete\n");
 
@@ -1708,6 +1731,7 @@ int radeon_driver_load(struct drm_device *dev, unsigned long flags)
        case CHIP_R300:
        case CHIP_R350:
        case CHIP_R420:
+       case CHIP_R423:
        case CHIP_RV410:
        case CHIP_RV515:
        case CHIP_R520: