drm/i915: Disable the GM965 MSI errata workaround.

[linux-2.6-omap-h63xx.git] / drivers / gpu / drm / i915 / i915_dma.c

diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 01de536e0211772ba3df3154af63e5cab652a1f4..553dd4bc307547cc1ac4928209c7f8b3423ce8a3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -154,6 +154,9 @@ static int i915_dma_cleanup(struct drm_device * dev)
        if (I915_NEED_GFX_HWS(dev))
                i915_free_hws(dev);
 
+       dev_priv->sarea = NULL;
+       dev_priv->sarea_priv = NULL;
+
        return 0;
 }
 
@@ -442,7 +445,7 @@ static void i915_emit_breadcrumb(struct drm_device *dev)
 
        BEGIN_LP_RING(4);
        OUT_RING(MI_STORE_DWORD_INDEX);
-       OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
+       OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
        OUT_RING(dev_priv->counter);
        OUT_RING(0);
        ADVANCE_LP_RING();
@@ -573,7 +576,7 @@ static int i915_dispatch_flip(struct drm_device * dev)
 
        BEGIN_LP_RING(4);
        OUT_RING(MI_STORE_DWORD_INDEX);
-       OUT_RING(5 << MI_STORE_DWORD_INDEX_SHIFT);
+       OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
        OUT_RING(dev_priv->counter);
        OUT_RING(0);
        ADVANCE_LP_RING();
@@ -608,7 +611,6 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
                            struct drm_file *file_priv)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-       u32 *hw_status = dev_priv->hw_status_page;
        drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
            dev_priv->sarea_priv;
        drm_i915_batchbuffer_t *batch = data;
@@ -634,7 +636,7 @@ static int i915_batchbuffer(struct drm_device *dev, void *data,
        mutex_unlock(&dev->struct_mutex);
 
        if (sarea_priv)
-               sarea_priv->last_dispatch = (int)hw_status[5];
+               sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
        return ret;
 }
 
@@ -642,7 +644,6 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
                          struct drm_file *file_priv)
 {
        drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
-       u32 *hw_status = dev_priv->hw_status_page;
        drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
            dev_priv->sarea_priv;
        drm_i915_cmdbuffer_t *cmdbuf = data;
@@ -670,7 +671,7 @@ static int i915_cmdbuffer(struct drm_device *dev, void *data,
        }
 
        if (sarea_priv)
-               sarea_priv->last_dispatch = (int)hw_status[5];
+               sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
        return 0;
 }
 
@@ -846,16 +847,23 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
         * and the registers being closely associated.
         *
         * According to chipset errata, on the 965GM, MSI interrupts may
-        * be lost or delayed
+        * be lost or delayed, but we use them anyways to avoid
+        * stuck interrupts on some machines.
         */
-       if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
-               if (pci_enable_msi(dev->pdev))
-                       DRM_ERROR("failed to enable MSI\n");
+       if (!IS_I945G(dev) && !IS_I945GM(dev))
+               pci_enable_msi(dev->pdev);
 
        intel_opregion_init(dev);
 
        spin_lock_init(&dev_priv->user_irq_lock);
 
+       ret = drm_vblank_init(dev, I915_NUM_PIPE);
+
+       if (ret) {
+               (void) i915_driver_unload(dev);
+               return ret;
+       }
+
        return ret;
 }
 
@@ -960,6 +968,7 @@ struct drm_ioctl_desc i915_ioctls[] = {
        DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
        DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
        DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
+       DRM_IOCTL_DEF(DRM_I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, 0),
 };
 
 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);