edac: i5100 fix unmask ecc bits

[linux-2.6-omap-h63xx.git] / drivers / edac / i5100_edac.c

diff --git a/drivers/edac/i5100_edac.c b/drivers/edac/i5100_edac.c
index 43430bf70181e59c623d78bf5acfe431f12acc00..d85e7992eb6ac29e032b1b5ded6de7309c101338 100644 (file)
--- a/drivers/edac/i5100_edac.c
+++ b/drivers/edac/i5100_edac.c
@@ -24,6 +24,8 @@
 /* register addresses and bit field accessors... */
 
 /* device 16, func 1 */
+#define I5100_MC               0x40    /* Memory Control Register */
+#define                I5100_MC_ERRDETEN(a)    ((a) >> 5 & 1)
 #define I5100_MS               0x44    /* Memory Status Register */
 #define I5100_SPDDATA          0x48    /* Serial Presence Detect Status Reg */
 #define                I5100_SPDDATA_RDO(a)    ((a) >> 15 & 1)
@@ -52,15 +54,28 @@
 #define                I5100_FERR_NF_MEM_M16ERR_MASK   (1 << 16)
 #define                I5100_FERR_NF_MEM_M15ERR_MASK   (1 << 15)
 #define                I5100_FERR_NF_MEM_M14ERR_MASK   (1 << 14)
-#define                I5100_FERR_NF_MEM_
-#define                I5100_FERR_NF_MEM_
+#define                I5100_FERR_NF_MEM_M12ERR_MASK   (1 << 12)
+#define                I5100_FERR_NF_MEM_M11ERR_MASK   (1 << 11)
+#define                I5100_FERR_NF_MEM_M10ERR_MASK   (1 << 10)
+#define                I5100_FERR_NF_MEM_M6ERR_MASK    (1 << 6)
+#define                I5100_FERR_NF_MEM_M5ERR_MASK    (1 << 5)
+#define                I5100_FERR_NF_MEM_M4ERR_MASK    (1 << 4)
+#define                I5100_FERR_NF_MEM_M1ERR_MASK    1
 #define                I5100_FERR_NF_MEM_ANY_MASK      \
                        (I5100_FERR_NF_MEM_M16ERR_MASK | \
                        I5100_FERR_NF_MEM_M15ERR_MASK | \
-                       I5100_FERR_NF_MEM_M14ERR_MASK)
+                       I5100_FERR_NF_MEM_M14ERR_MASK | \
+                       I5100_FERR_NF_MEM_M12ERR_MASK | \
+                       I5100_FERR_NF_MEM_M11ERR_MASK | \
+                       I5100_FERR_NF_MEM_M10ERR_MASK | \
+                       I5100_FERR_NF_MEM_M6ERR_MASK | \
+                       I5100_FERR_NF_MEM_M5ERR_MASK | \
+                       I5100_FERR_NF_MEM_M4ERR_MASK | \
+                       I5100_FERR_NF_MEM_M1ERR_MASK)
 #define                I5100_FERR_NF_MEM_ANY(a)  ((a) & I5100_FERR_NF_MEM_ANY_MASK)
 #define        I5100_NERR_NF_MEM       0xa4    /* MC Next Non-Fatal Errors */
 #define                I5100_NERR_NF_MEM_ANY(a)  I5100_FERR_NF_MEM_ANY(a)
+#define I5100_EMASK_MEM                0xa8    /* MC Error Mask Register */
 
 /* device 21 and 22, func 0 */
 #define I5100_MTR_0    0x154   /* Memory Technology Registers 0-3 */
@@ -676,6 +691,14 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
                goto bail;
        }
 
+       /* ECC enabled? */
+       pci_read_config_dword(pdev, I5100_MC, &dw);
+       if (!I5100_MC_ERRDETEN(dw)) {
+               printk(KERN_INFO "i5100_edac: ECC not enabled.\n");
+               ret = -ENODEV;
+               goto bail;
+       }
+
        /* figure out how many ranks, from strapped state of 48GB_Mode input */
        pci_read_config_dword(pdev, I5100_MS, &dw);
        ranksperch = !!(dw & (1 << 8)) * 2 + 4;
@@ -687,6 +710,11 @@ static int __devinit i5100_init_one(struct pci_dev *pdev,
                goto bail;
        }
 
+       /* enable error reporting... */
+       pci_read_config_dword(pdev, I5100_EMASK_MEM, &dw);
+       dw &= ~I5100_FERR_NF_MEM_ANY_MASK;
+       pci_write_config_dword(pdev, I5100_EMASK_MEM, dw);
+
        /* device 21, func 0, Channel 0 Memory Map, Error Flag/Mask, etc... */
        ch0mm = pci_get_device_func(PCI_VENDOR_ID_INTEL,
                                    PCI_DEVICE_ID_INTEL_5100_21, 0);