drm/i915 more registers for S3 (DSPCLK_GATE_D, CACHE_MODE_0, MI_ARB_STATE)

[linux-2.6-omap-h63xx.git] / drivers / char / drm / i915_drv.h

diff --git a/drivers/char/drm/i915_drv.h b/drivers/char/drm/i915_drv.h
index 360f6600427b21919f93b9a39b4129ec01eb6b56..c10d128e34dbd08beb949eef706d3ab11cee3a71 100644 (file)
--- a/drivers/char/drm/i915_drv.h
+++ b/drivers/char/drm/i915_drv.h
@@ -187,6 +187,9 @@ typedef struct drm_i915_private {
        u32 saveIER;
        u32 saveIIR;
        u32 saveIMR;
+       u32 saveCACHE_MODE_0;
+       u32 saveDSPCLK_GATE_D;
+       u32 saveMI_ARB_STATE;
        u32 saveSWF0[16];
        u32 saveSWF1[16];
        u32 saveSWF2[3];
@@ -455,6 +458,10 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
  */
 #define DMA_FADD_S             0x20d4
 
+/* Memory Interface Arbitration State
+ */
+#define MI_ARB_STATE           0x20e4
+
 /* Cache mode 0 reg.
  *  - Manipulating render cache behaviour is central
  *    to the concept of zone rendering, tuning this reg can help avoid
@@ -465,6 +472,7 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
  * bit of interest either set or cleared.  EG: (BIT<<16) | BIT to set.
  */
 #define Cache_Mode_0           0x2120
+#define CACHE_MODE_0           0x2120
 #define CM0_MASK_SHIFT          16
 #define CM0_IZ_OPT_DISABLE      (1<<6)
 #define CM0_ZR_OPT_DISABLE      (1<<5)
@@ -660,6 +668,8 @@ extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
 /** P1 value is 2 greater than this field */
 # define VGA0_PD_P1_MASK       (0x1f << 0)
 
+#define DSPCLK_GATE_D  0x6200
+
 /* I830 CRTC registers */
 #define HTOTAL_A       0x60000
 #define HBLANK_A       0x60004