x86: c_p_a() fix: reorder TLB / cache flushes to follow Intel recommendation

[linux-2.6-omap-h63xx.git] / arch / x86 / mm / pageattr_64.c

diff --git a/arch/x86/mm/pageattr_64.c b/arch/x86/mm/pageattr_64.c
index 4d172881af7012f5255d6265563ec5ebea99b002..3ccdb1401e673c219ac7f8aafb208da012b182a0 100644 (file)
--- a/arch/x86/mm/pageattr_64.c
+++ b/arch/x86/mm/pageattr_64.c
@@ -82,6 +82,8 @@ static void flush_kernel_map(void *arg)
        struct list_head *l = (struct list_head *)arg;
        struct page *pg;
 
+       __flush_tlb_all();
+
        /* When clflush is available always use it because it is
           much cheaper than WBINVD. */
        /* clflush is still broken. Disable for now. */
@@ -94,7 +96,6 @@ static void flush_kernel_map(void *arg)
                        clflush_cache_range(addr, PAGE_SIZE);
                }
        }
-       __flush_tlb_all();
 }
 
 static inline void flush_map(struct list_head *l)