x86, gart: add resume handling

[linux-2.6-omap-h63xx.git] / arch / x86 / kernel / pci-gart_64.c

diff --git a/arch/x86/kernel/pci-gart_64.c b/arch/x86/kernel/pci-gart_64.c
index 700e4647dd30214ba33b90845f4121421515948d..f505c38903583dad2a856a2d7c3933f7d539b183 100644 (file)
--- a/arch/x86/kernel/pci-gart_64.c
+++ b/arch/x86/kernel/pci-gart_64.c
@@ -26,6 +26,7 @@
 #include <linux/kdebug.h>
 #include <linux/scatterlist.h>
 #include <linux/iommu-helper.h>
+#include <linux/sysdev.h>
 #include <asm/atomic.h>
 #include <asm/io.h>
 #include <asm/mtrr.h>
@@ -264,9 +265,9 @@ static dma_addr_t dma_map_area(struct device *dev, dma_addr_t phys_mem,
 }
 
 static dma_addr_t
-gart_map_simple(struct device *dev, char *buf, size_t size, int dir)
+gart_map_simple(struct device *dev, phys_addr_t paddr, size_t size, int dir)
 {
-       dma_addr_t map = dma_map_area(dev, virt_to_bus(buf), size, dir);
+       dma_addr_t map = dma_map_area(dev, paddr, size, dir);
 
        flush_gart();
 
@@ -275,18 +276,17 @@ gart_map_simple(struct device *dev, char *buf, size_t size, int dir)
 
 /* Map a single area into the IOMMU */
 static dma_addr_t
-gart_map_single(struct device *dev, void *addr, size_t size, int dir)
+gart_map_single(struct device *dev, phys_addr_t paddr, size_t size, int dir)
 {
-       unsigned long phys_mem, bus;
+       unsigned long bus;
 
        if (!dev)
                dev = &fallback_dev;
 
-       phys_mem = virt_to_phys(addr);
-       if (!need_iommu(dev, phys_mem, size))
-               return phys_mem;
+       if (!need_iommu(dev, paddr, size))
+               return paddr;
 
-       bus = gart_map_simple(dev, addr, size, dir);
+       bus = gart_map_simple(dev, paddr, size, dir);
 
        return bus;
 }
@@ -534,8 +534,8 @@ static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
        unsigned aper_size = 0, aper_base_32, aper_order;
        u64 aper_base;
 
-       pci_read_config_dword(dev, 0x94, &aper_base_32);
-       pci_read_config_dword(dev, 0x90, &aper_order);
+       pci_read_config_dword(dev, AMD64_GARTAPERTUREBASE, &aper_base_32);
+       pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &aper_order);
        aper_order = (aper_order >> 1) & 7;
 
        aper_base = aper_base_32 & 0x7fff;
@@ -549,6 +549,77 @@ static __init unsigned read_aperture(struct pci_dev *dev, u32 *size)
        return aper_base;
 }
 
+static void enable_gart_translations(void)
+{
+       int i;
+
+       for (i = 0; i < num_k8_northbridges; i++) {
+               struct pci_dev *dev = k8_northbridges[i];
+
+               enable_gart_translation(dev, __pa(agp_gatt_table));
+       }
+}
+
+/*
+ * If fix_up_north_bridges is set, the north bridges have to be fixed up on
+ * resume in the same way as they are handled in gart_iommu_hole_init().
+ */
+static bool fix_up_north_bridges;
+static u32 aperture_order;
+static u32 aperture_alloc;
+
+void set_up_gart_resume(u32 aper_order, u32 aper_alloc)
+{
+       fix_up_north_bridges = true;
+       aperture_order = aper_order;
+       aperture_alloc = aper_alloc;
+}
+
+static int gart_resume(struct sys_device *dev)
+{
+       printk(KERN_INFO "PCI-DMA: Resuming GART IOMMU\n");
+
+       if (fix_up_north_bridges) {
+               int i;
+
+               printk(KERN_INFO "PCI-DMA: Restoring GART aperture settings\n");
+
+               for (i = 0; i < num_k8_northbridges; i++) {
+                       struct pci_dev *dev = k8_northbridges[i];
+
+                       /*
+                        * Don't enable translations just yet.  That is the next
+                        * step.  Restore the pre-suspend aperture settings.
+                        */
+                       pci_write_config_dword(dev, AMD64_GARTAPERTURECTL,
+                                               aperture_order << 1);
+                       pci_write_config_dword(dev, AMD64_GARTAPERTUREBASE,
+                                               aperture_alloc >> 25);
+               }
+       }
+
+       enable_gart_translations();
+
+       return 0;
+}
+
+static int gart_suspend(struct sys_device *dev, pm_message_t state)
+{
+       return 0;
+}
+
+static struct sysdev_class gart_sysdev_class = {
+       .name = "gart",
+       .suspend = gart_suspend,
+       .resume = gart_resume,
+
+};
+
+static struct sys_device device_gart = {
+       .id     = 0,
+       .cls    = &gart_sysdev_class,
+};
+
 /*
  * Private Northbridge GATT initialization in case we cannot use the
  * AGP driver for some reason.
@@ -559,7 +630,7 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
        unsigned aper_base, new_aper_base;
        struct pci_dev *dev;
        void *gatt;
-       int i;
+       int i, error;
 
        printk(KERN_INFO "PCI-DMA: Disabling AGP.\n");
        aper_size = aper_base = info->aper_size = 0;
@@ -592,21 +663,14 @@ static __init int init_k8_gatt(struct agp_kern_info *info)
        memset(gatt, 0, gatt_size);
        agp_gatt_table = gatt;
 
-       for (i = 0; i < num_k8_northbridges; i++) {
-               u32 gatt_reg;
-               u32 ctl;
+       enable_gart_translations();
 
-               dev = k8_northbridges[i];
-               gatt_reg = __pa(gatt) >> 12;
-               gatt_reg <<= 4;
-               pci_write_config_dword(dev, 0x98, gatt_reg);
-               pci_read_config_dword(dev, 0x90, &ctl);
+       error = sysdev_class_register(&gart_sysdev_class);
+       if (!error)
+               error = sysdev_register(&device_gart);
+       if (error)
+               panic("Could not register gart_sysdev -- would corrupt data on next suspend");
 
-               ctl |= 1;
-               ctl &= ~((1<<4) | (1<<5));
-
-               pci_write_config_dword(dev, 0x90, ctl);
-       }
        flush_gart();
 
        printk(KERN_INFO "PCI-DMA: aperture base @ %x size %u KB\n",
@@ -649,11 +713,11 @@ void gart_iommu_shutdown(void)
                u32 ctl;
 
                dev = k8_northbridges[i];
-               pci_read_config_dword(dev, 0x90, &ctl);
+               pci_read_config_dword(dev, AMD64_GARTAPERTURECTL, &ctl);
 
-               ctl &= ~1;
+               ctl &= ~GARTEN;
 
-               pci_write_config_dword(dev, 0x90, ctl);
+               pci_write_config_dword(dev, AMD64_GARTAPERTURECTL, ctl);
        }
 }