x86: I/O APIC: timer through 8259A second-chance

[linux-2.6-omap-h63xx.git] / arch / x86 / kernel / io_apic_32.c

diff --git a/arch/x86/kernel/io_apic_32.c b/arch/x86/kernel/io_apic_32.c
index 41218ac75d103bf45bfddfb19cddc700393b42f2..a69a59d19e187999184a398fa28af9828167c20f 100644 (file)
--- a/arch/x86/kernel/io_apic_32.c
+++ b/arch/x86/kernel/io_apic_32.c
@@ -58,6 +58,7 @@ static struct { int pin, apic; } ioapic_i8259 = { -1, -1 };
 static DEFINE_SPINLOCK(ioapic_lock);
 static DEFINE_SPINLOCK(vector_lock);
 
+int timer_through_8259 __initdata;
 
 /*
  *     Is the SiS APIC rmw bug present ?
@@ -1301,25 +1302,21 @@ static void __init setup_IO_APIC_irqs(void)
 }
 
 /*
- * Set up the 8259A-master output pin:
+ * Set up the timer pin, possibly with the 8259A-master behind.
  */
-static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, int vector)
+static void __init setup_timer_IRQ0_pin(unsigned int apic, unsigned int pin,
+                                       int vector)
 {
        struct IO_APIC_route_entry entry;
 
        memset(&entry,0,sizeof(entry));
 
-       disable_8259A_irq(0);
-
-       /* mask LVT0 */
-       apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
-
        /*
         * We use logical delivery to get the timer IRQ
         * to the first CPU.
         */
        entry.dest_mode = INT_DEST_MODE;
-       entry.mask = 0;                                 /* unmask IRQ now */
+       entry.mask = 1;                                 /* mask IRQ now */
        entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
        entry.delivery_mode = INT_DELIVERY_MODE;
        entry.polarity = 0;
@@ -1328,17 +1325,14 @@ static void __init setup_ExtINT_IRQ0_pin(unsigned int apic, unsigned int pin, in
 
        /*
         * The timer IRQ doesn't have to know that behind the
-        * scene we have a 8259A-master in AEOI mode ...
+        * scene we may have a 8259A-master in AEOI mode ...
         */
-       irq_desc[0].chip = &ioapic_chip;
-       set_irq_handler(0, handle_edge_irq);
+       ioapic_register_intr(0, vector, IOAPIC_EDGE);
 
        /*
         * Add it to the IO-APIC irq-routing table:
         */
        ioapic_write_entry(apic, pin, entry);
-
-       enable_8259A_irq(0);
 }
 
 void __init print_IO_APIC(void)
@@ -2036,7 +2030,7 @@ static void unmask_lapic_irq (unsigned int irq)
 }
 
 static struct irq_chip lapic_chip __read_mostly = {
-       .name           = "local-APIC-edge",
+       .name           = "local-APIC",
        .mask           = mask_lapic_irq,
        .unmask         = unmask_lapic_irq,
        .eoi            = ack_apic,
@@ -2128,6 +2122,7 @@ static inline void __init unlock_ExtINT_logic(void)
 static inline void __init check_timer(void)
 {
        int apic1, pin1, apic2, pin2;
+       int no_pin1 = 0;
        int vector;
        unsigned int ver;
        unsigned long flags;
@@ -2165,10 +2160,30 @@ static inline void __init check_timer(void)
        printk(KERN_INFO "..TIMER: vector=0x%02X apic1=%d pin1=%d apic2=%d pin2=%d\n",
                vector, apic1, pin1, apic2, pin2);
 
+       /*
+        * Some BIOS writers are clueless and report the ExtINTA
+        * I/O APIC input from the cascaded 8259A as the timer
+        * interrupt input.  So just in case, if only one pin
+        * was found above, try it both directly and through the
+        * 8259A.
+        */
+       if (pin1 == -1) {
+               pin1 = pin2;
+               apic1 = apic2;
+               no_pin1 = 1;
+       } else if (pin2 == -1) {
+               pin2 = pin1;
+               apic2 = apic1;
+       }
+
        if (pin1 != -1) {
                /*
                 * Ok, does IRQ0 through the IOAPIC work?
                 */
+               if (no_pin1) {
+                       add_pin_to_irq(0, apic1, pin1);
+                       setup_timer_IRQ0_pin(apic1, pin1, vector);
+               }
                unmask_IO_APIC_irq(0);
                if (timer_irq_works()) {
                        if (nmi_watchdog == NMI_IO_APIC) {
@@ -2180,24 +2195,23 @@ static inline void __init check_timer(void)
                        goto out;
                }
                clear_IO_APIC_pin(apic1, pin1);
-               printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to "
-                               "IO-APIC\n");
-       }
+               if (!no_pin1)
+                       printk(KERN_ERR "..MP-BIOS bug: "
+                              "8254 timer not connected to IO-APIC\n");
 
-       printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
-       if (pin2 != -1) {
+               printk(KERN_INFO "...trying to set up timer (IRQ0) "
+                      "through the 8259A ... ");
                printk("\n..... (found pin %d) ...", pin2);
                /*
                 * legacy devices should be connected to IO APIC #0
                 */
-               setup_ExtINT_IRQ0_pin(apic2, pin2, vector);
+               replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
+               setup_timer_IRQ0_pin(apic2, pin2, vector);
+               unmask_IO_APIC_irq(0);
                enable_8259A_irq(0);
                if (timer_irq_works()) {
                        printk("works.\n");
-                       if (pin1 != -1)
-                               replace_pin_at_irq(0, apic1, pin1, apic2, pin2);
-                       else
-                               add_pin_to_irq(0, apic2, pin2);
+                       timer_through_8259 = 1;
                        if (nmi_watchdog == NMI_IO_APIC) {
                                disable_8259A_irq(0);
                                setup_nmi();
@@ -2210,8 +2224,8 @@ static inline void __init check_timer(void)
                 */
                disable_8259A_irq(0);
                clear_IO_APIC_pin(apic2, pin2);
+               printk(" failed.\n");
        }
-       printk(" failed.\n");
 
        if (nmi_watchdog == NMI_IO_APIC) {
                printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");