Merge branches 'x86/asm', 'x86/cleanups', 'x86/cpudetect', 'x86/debug', 'x86/doc...

[linux-2.6-omap-h63xx.git] / arch / x86 / kernel / cpu / intel.c

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 549f2ada55f584bd045e13fb1e0c65a029f317e1..5deefae9064dcba2fdfa11265abf37f79c4b3978 100644 (file)
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -30,7 +30,7 @@
 static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
 {
        /* Unmask CPUID levels if masked: */
-       if (c->x86 == 6 && c->x86_model >= 15) {
+       if (c->x86 > 6 || (c->x86 == 6 && c->x86_model >= 0xd)) {
                u64 misc_enable;
 
                rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable);
@@ -63,6 +63,18 @@ static void __cpuinit early_init_intel(struct cpuinfo_x86 *c)
                set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
        }
 
+       /*
+        * There is a known erratum on Pentium III and Core Solo
+        * and Core Duo CPUs.
+        * " Page with PAT set to WC while associated MTRR is UC
+        *   may consolidate to UC "
+        * Because of this erratum, it is better to stick with
+        * setting WC in MTRR rather than using PAT on these CPUs.
+        *
+        * Enable PAT WC only on P4, Core 2 or later CPUs.
+        */
+       if (c->x86 == 6 && c->x86_model < 15)
+               clear_cpu_cap(c, X86_FEATURE_PAT);
 }
 
 #ifdef CONFIG_X86_32