Driver core: change sysdev classes to use dynamic kobject names

[linux-2.6-omap-h63xx.git] / arch / x86 / kernel / apic_64.c

diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index 1231365404c4eb809d307c4e7d39b0bdcfb98f56..fa6cdee6d303a9dbd29b9f198fd2742140ebc0d8 100644 (file)
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -41,9 +41,8 @@
 #include <asm/apic.h>
 
 int apic_verbosity;
-int apic_calibrate_pmtmr __initdata;
-
 int disable_apic_timer __cpuinitdata;
+static int apic_calibrate_pmtmr __initdata;
 
 /* Local APIC timer works in C2? */
 int local_apic_timer_c2_ok;
@@ -247,7 +246,10 @@ void disconnect_bsp_APIC(int virt_wire_setup)
        apic_write(APIC_SPIV, value);
 
        if (!virt_wire_setup) {
-               /* For LVT0 make it edge triggered, active high, external and enabled */
+               /*
+                * For LVT0 make it edge triggered, active high,
+                * external and enabled
+                */
                value = apic_read(APIC_LVT0);
                value &= ~(APIC_MODE_MASK | APIC_SEND_PENDING |
                        APIC_INPUT_POLARITY | APIC_LVT_REMOTE_IRR |
@@ -285,6 +287,20 @@ void disable_local_APIC(void)
        apic_write(APIC_SPIV, value);
 }
 
+void lapic_shutdown(void)
+{
+       unsigned long flags;
+
+       if (!cpu_has_apic)
+               return;
+
+       local_irq_save(flags);
+
+       disable_local_APIC();
+
+       local_irq_restore(flags);
+}
+
 /*
  * This is to verify that we're looking at a real local APIC.
  * Check these against your board if the CPUs aren't getting
@@ -483,10 +499,12 @@ void __cpuinit setup_local_APIC (void)
        value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
        if (!smp_processor_id() && !value) {
                value = APIC_DM_EXTINT;
-               apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
+               apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n",
+                           smp_processor_id());
        } else {
                value = APIC_DM_EXTINT | APIC_LVT_MASKED;
-               apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
+               apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n",
+                           smp_processor_id());
        }
        apic_write(APIC_LVT0, value);
 
@@ -621,7 +639,7 @@ static int lapic_resume(struct sys_device *dev)
 }
 
 static struct sysdev_class lapic_sysclass = {
-       set_kset_name("lapic"),
+       .name           = "lapic",
        .resume         = lapic_resume,
        .suspend        = lapic_suspend,
 };
@@ -793,12 +811,14 @@ void __init init_apic_mappings(void)
                        if (smp_found_config) {
                                ioapic_phys = mp_ioapics[i].mpc_apicaddr;
                        } else {
-                               ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
+                               ioapic_phys = (unsigned long)
+                                       alloc_bootmem_pages(PAGE_SIZE);
                                ioapic_phys = __pa(ioapic_phys);
                        }
                        set_fixmap_nocache(idx, ioapic_phys);
-                       apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n",
-                                       __fix_to_virt(idx), ioapic_phys);
+                       apic_printk(APIC_VERBOSE,
+                                   "mapped IOAPIC to %016lx (%016lx)\n",
+                                   __fix_to_virt(idx), ioapic_phys);
                        idx++;
 
                        if (ioapic_res != NULL) {
@@ -958,8 +978,31 @@ void __init setup_boot_APIC_clock (void)
        setup_APIC_timer();
 }
 
+/*
+ * AMD C1E enabled CPUs have a real nasty problem: Some BIOSes set the
+ * C1E flag only in the secondary CPU, so when we detect the wreckage
+ * we already have enabled the boot CPU local apic timer. Check, if
+ * disable_apic_timer is set and the DUMMY flag is cleared. If yes,
+ * set the DUMMY flag again and force the broadcast mode in the
+ * clockevents layer.
+ */
+void __cpuinit check_boot_apic_timer_broadcast(void)
+{
+       if (!disable_apic_timer ||
+           (lapic_clockevent.features & CLOCK_EVT_FEAT_DUMMY))
+               return;
+
+       printk(KERN_INFO "AMD C1E detected late. Force timer broadcast.\n");
+       lapic_clockevent.features |= CLOCK_EVT_FEAT_DUMMY;
+
+       local_irq_enable();
+       clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE, &boot_cpu_id);
+       local_irq_disable();
+}
+
 void __cpuinit setup_secondary_APIC_clock(void)
 {
+       check_boot_apic_timer_broadcast();
        setup_APIC_timer();
 }
 
@@ -1111,6 +1154,7 @@ asmlinkage void smp_spurious_interrupt(void)
        if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
                ack_APIC_irq();
 
+       add_pda(irq_spurious_count, 1);
        irq_exit();
 }