x86: apic - unify lapic_resume

[linux-2.6-omap-h63xx.git] / arch / x86 / kernel / apic_64.c

diff --git a/arch/x86/kernel/apic_64.c b/arch/x86/kernel/apic_64.c
index d834b7583624c885c41390375e40fbaa7b6f9b99..e542a2d08de5eb186ae4a110836542e352d6d1e0 100644 (file)
--- a/arch/x86/kernel/apic_64.c
+++ b/arch/x86/kernel/apic_64.c
@@ -1412,13 +1412,22 @@ static int lapic_resume(struct sys_device *dev)
        maxlvt = lapic_get_maxlvt();
 
        local_irq_save(flags);
-       if (!x2apic) {
+
+#ifdef CONFIG_X86_64
+       if (x2apic)
+               enable_x2apic();
+       else
+#endif
+               /*
+                * Make sure the APICBASE points to the right address
+                *
+                * FIXME! This will be wrong if we ever support suspend on
+                * SMP! We'll need to do this as part of the CPU restore!
+                */
                rdmsr(MSR_IA32_APICBASE, l, h);
                l &= ~MSR_IA32_APICBASE_BASE;
                l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
                wrmsr(MSR_IA32_APICBASE, l, h);
-       } else
-               enable_x2apic();
 
        apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
        apic_write(APIC_ID, apic_pm_state.apic_id);
@@ -1428,7 +1437,7 @@ static int lapic_resume(struct sys_device *dev)
        apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
        apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
        apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
-#ifdef CONFIG_X86_MCE_INTEL
+#if defined(CONFIG_X86_MCE_P4THERMAL) || defined(CONFIG_X86_MCE_INTEL)
        if (maxlvt >= 5)
                apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
 #endif
@@ -1442,7 +1451,9 @@ static int lapic_resume(struct sys_device *dev)
        apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
        apic_write(APIC_ESR, 0);
        apic_read(APIC_ESR);
+
        local_irq_restore(flags);
+
        return 0;
 }