#include <asm/pgtable.h>
#include <asm/irq.h>
#include <asm/ebus.h>
-#include <asm/isa.h>
#include <asm/prom.h>
#include <asm/apb.h>
struct pci_dev *of_create_pci_dev(struct pci_pbm_info *pbm,
struct device_node *node,
- struct pci_bus *bus, int devfn,
- int host_controller)
+ struct pci_bus *bus, int devfn)
{
struct dev_archdata *sd;
struct pci_dev *dev;
dev->devfn = devfn;
dev->multifunction = 0; /* maybe a lie? */
- if (host_controller) {
- if (tlb_type != hypervisor) {
- pci_read_config_word(dev, PCI_VENDOR_ID,
- &dev->vendor);
- pci_read_config_word(dev, PCI_DEVICE_ID,
- &dev->device);
- } else {
- dev->vendor = PCI_VENDOR_ID_SUN;
- dev->device = 0x80f0;
- }
- dev->cfg_size = 256;
- dev->class = PCI_CLASS_BRIDGE_HOST << 8;
- sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
- 0x00, PCI_SLOT(devfn), PCI_FUNC(devfn));
- } else {
- dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
- dev->device = of_getintprop_default(node, "device-id", 0xffff);
- dev->subsystem_vendor =
- of_getintprop_default(node, "subsystem-vendor-id", 0);
- dev->subsystem_device =
- of_getintprop_default(node, "subsystem-id", 0);
-
- dev->cfg_size = pci_cfg_space_size(dev);
-
- /* We can't actually use the firmware value, we have
- * to read what is in the register right now. One
- * reason is that in the case of IDE interfaces the
- * firmware can sample the value before the the IDE
- * interface is programmed into native mode.
- */
- pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
- dev->class = class >> 8;
- dev->revision = class & 0xff;
+ dev->vendor = of_getintprop_default(node, "vendor-id", 0xffff);
+ dev->device = of_getintprop_default(node, "device-id", 0xffff);
+ dev->subsystem_vendor =
+ of_getintprop_default(node, "subsystem-vendor-id", 0);
+ dev->subsystem_device =
+ of_getintprop_default(node, "subsystem-id", 0);
+
+ dev->cfg_size = pci_cfg_space_size(dev);
+
+ /* We can't actually use the firmware value, we have
+ * to read what is in the register right now. One
+ * reason is that in the case of IDE interfaces the
+ * firmware can sample the value before the the IDE
+ * interface is programmed into native mode.
+ */
+ pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
+ dev->class = class >> 8;
+ dev->revision = class & 0xff;
+
+ dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(bus),
+ dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
- sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(bus),
- dev->bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn));
- }
if (ofpci_verbose)
printk(" class: 0x%x device name: %s\n",
dev->class, pci_name(dev));
dev->current_state = 4; /* unknown power state */
dev->error_state = pci_channel_io_normal;
- if (host_controller) {
+ if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
+ /* a PCI-PCI bridge */
dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
dev->rom_base_reg = PCI_ROM_ADDRESS1;
- dev->irq = PCI_IRQ_NONE;
+ } else if (!strcmp(type, "cardbus")) {
+ dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
} else {
- if (!strcmp(type, "pci") || !strcmp(type, "pciex")) {
- /* a PCI-PCI bridge */
- dev->hdr_type = PCI_HEADER_TYPE_BRIDGE;
- dev->rom_base_reg = PCI_ROM_ADDRESS1;
- } else if (!strcmp(type, "cardbus")) {
- dev->hdr_type = PCI_HEADER_TYPE_CARDBUS;
- } else {
- dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
- dev->rom_base_reg = PCI_ROM_ADDRESS;
+ dev->hdr_type = PCI_HEADER_TYPE_NORMAL;
+ dev->rom_base_reg = PCI_ROM_ADDRESS;
- dev->irq = sd->op->irqs[0];
- if (dev->irq == 0xffffffff)
- dev->irq = PCI_IRQ_NONE;
- }
+ dev->irq = sd->op->irqs[0];
+ if (dev->irq == 0xffffffff)
+ dev->irq = PCI_IRQ_NONE;
}
+
pci_parse_of_addrs(sd->op, node, dev);
if (ofpci_verbose)
prev_devfn = devfn;
/* create a new pci_dev for this device */
- dev = of_create_pci_dev(pbm, child, bus, devfn, 0);
+ dev = of_create_pci_dev(pbm, child, bus, devfn);
if (!dev)
continue;
if (ofpci_verbose)
pci_bus_register_of_sysfs(child_bus);
}
-int pci_host_bridge_read_pci_cfg(struct pci_bus *bus_dev,
- unsigned int devfn,
- int where, int size,
- u32 *value)
-{
- static u8 fake_pci_config[] = {
- 0x8e, 0x10, /* Vendor: 0x108e (Sun) */
- 0xf0, 0x80, /* Device: 0x80f0 (Fire) */
- 0x46, 0x01, /* Command: 0x0146 (SERR, PARITY, MASTER, MEM) */
- 0xa0, 0x22, /* Status: 0x02a0 (DEVSEL_MED, FB2B, 66MHZ) */
- 0x00, 0x00, 0x00, 0x06, /* Class: 0x06000000 host bridge */
- 0x00, /* Cacheline: 0x00 */
- 0x40, /* Latency: 0x40 */
- 0x00, /* Header-Type: 0x00 normal */
- };
-
- *value = 0;
- if (where >= 0 && where < sizeof(fake_pci_config) &&
- (where + size) >= 0 &&
- (where + size) < sizeof(fake_pci_config) &&
- size <= sizeof(u32)) {
- while (size--) {
- *value <<= 8;
- *value |= fake_pci_config[where + size];
- }
- }
-
- return PCIBIOS_SUCCESSFUL;
-}
-
-int pci_host_bridge_write_pci_cfg(struct pci_bus *bus_dev,
- unsigned int devfn,
- int where, int size,
- u32 value)
-{
- return PCIBIOS_SUCCESSFUL;
-}
-
struct pci_bus * __devinit pci_scan_one_pbm(struct pci_pbm_info *pbm)
{
struct device_node *node = pbm->prom_node;
- struct pci_dev *host_pdev;
struct pci_bus *bus;
printk("PCI: Scanning PBM %s\n", node->full_name);
bus->resource[0] = &pbm->io_space;
bus->resource[1] = &pbm->mem_space;
- /* Create the dummy host bridge and link it in. */
- host_pdev = of_create_pci_dev(pbm, node, bus, 0x00, 1);
- bus->self = host_pdev;
-
pci_of_scan_bus(pbm, node, bus);
pci_bus_add_devices(bus);
pci_bus_register_of_sysfs(bus);
pci_scan_each_controller_bus();
- isa_init();
ebus_init();
power_init();
projects / linux-2.6-omap-h63xx.git / blobdiff