[PATCH] powerpc: properly configure DDR/P5IOC children devs

[linux-2.6-omap-h63xx.git] / arch / powerpc / platforms / pseries / pci_dlpar.c

diff --git a/arch/powerpc/platforms/pseries/pci_dlpar.c b/arch/powerpc/platforms/pseries/pci_dlpar.c
index bdaa8aabdaa64c4388c5ca4d933464a0293aa6f0..44abdeb9ca03151f6ed6fbe77b8682f0488ed14b 100644 (file)
--- a/arch/powerpc/platforms/pseries/pci_dlpar.c
+++ b/arch/powerpc/platforms/pseries/pci_dlpar.c
@@ -27,6 +27,7 @@
 
 #include <linux/pci.h>
 #include <asm/pci-bridge.h>
+#include <asm/ppc-pci.h>
 
 static struct pci_bus *
 find_bus_among_children(struct pci_bus *bus,
@@ -106,6 +107,8 @@ pcibios_fixup_new_pci_devices(struct pci_bus *bus, int fix_bus)
                        }
                }
        }
+
+       eeh_add_device_tree_late(bus);
 }
 EXPORT_SYMBOL_GPL(pcibios_fixup_new_pci_devices);
 
@@ -114,7 +117,6 @@ pcibios_pci_config_bridge(struct pci_dev *dev)
 {
        u8 sec_busno;
        struct pci_bus *child_bus;
-       struct pci_dev *child_dev;
 
        /* Get busno of downstream bus */
        pci_read_config_byte(dev, PCI_SECONDARY_BUS, &sec_busno);
@@ -129,10 +131,6 @@ pcibios_pci_config_bridge(struct pci_dev *dev)
 
        pci_scan_child_bus(child_bus);
 
-       list_for_each_entry(child_dev, &child_bus->devices, bus_list) {
-               eeh_add_device_late(child_dev);
-       }
-
        /* Fixup new pci devices without touching bus struct */
        pcibios_fixup_new_pci_devices(child_bus, 0);
 
@@ -160,18 +158,52 @@ pcibios_add_pci_devices(struct pci_bus * bus)
 
        eeh_add_device_tree_early(dn);
 
-       /* pci_scan_slot should find all children */
-       slotno = PCI_SLOT(PCI_DN(dn->child)->devfn);
-       num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
-       if (num) {
-               pcibios_fixup_new_pci_devices(bus, 1);
-               pci_bus_add_devices(bus);
-       }
+       if (_machine == PLATFORM_PSERIES_LPAR) {
+               /* use ofdt-based probe */
+               of_scan_bus(dn, bus);
+               if (!list_empty(&bus->devices)) {
+                       pcibios_fixup_new_pci_devices(bus, 0);
+                       pci_bus_add_devices(bus);
+               }
+       } else {
+               /* use legacy probe */
+               slotno = PCI_SLOT(PCI_DN(dn->child)->devfn);
+               num = pci_scan_slot(bus, PCI_DEVFN(slotno, 0));
+               if (num) {
+                       pcibios_fixup_new_pci_devices(bus, 1);
+                       pci_bus_add_devices(bus);
+               }
 
-       list_for_each_entry(dev, &bus->devices, bus_list) {
-               eeh_add_device_late (dev);
-               if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
-                       pcibios_pci_config_bridge(dev);
+               list_for_each_entry(dev, &bus->devices, bus_list)
+                       if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
+                               pcibios_pci_config_bridge(dev);
        }
 }
 EXPORT_SYMBOL_GPL(pcibios_add_pci_devices);
+
+struct pci_controller * __devinit init_phb_dynamic(struct device_node *dn)
+{
+       struct pci_controller *phb;
+       int primary;
+
+       primary = list_empty(&hose_list);
+       phb = pcibios_alloc_controller(dn);
+       if (!phb)
+               return NULL;
+       setup_phb(dn, phb);
+       pci_process_bridge_OF_ranges(phb, dn, 0);
+
+       pci_setup_phb_io_dynamic(phb, primary);
+
+       pci_devs_phb_init_dynamic(phb);
+
+       if (dn->child)
+               eeh_add_device_tree_early(dn);
+
+       scan_phb(phb);
+       pcibios_fixup_new_pci_devices(phb->bus, 0);
+       pci_bus_add_devices(phb->bus);
+
+       return phb;
+}
+EXPORT_SYMBOL_GPL(init_phb_dynamic);