#define MPIC_NO_BIAS 0x00000400
/* Ignore NIRQS as reported by FRR */
#define MPIC_BROKEN_FRR_NIRQS 0x00000800
+/* Destination only supports a single CPU at a time */
+#define MPIC_SINGLE_DEST_CPU 0x00001000
/* MPIC HW modification ID */
#define MPIC_REGSET_MASK 0xf0000000