[MIPS] Rewrite all the assembler interrupt handlers to C.

[linux-2.6-omap-h63xx.git] / arch / mips / vr41xx / common / irq.c

diff --git a/arch/mips/vr41xx/common/irq.c b/arch/mips/vr41xx/common/irq.c
index 61aa264275ff2883d0f1fbec5871645a307a5287..86796bb63c3c7e3d6b3aaa41626a52a43b8eca35 100644 (file)
--- a/arch/mips/vr41xx/common/irq.c
+++ b/arch/mips/vr41xx/common/irq.c
@@ -59,7 +59,7 @@ int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int, struct pt_regs *)
 
 EXPORT_SYMBOL_GPL(cascade_irq);
 
-asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs)
+static void irq_dispatch(unsigned int irq, struct pt_regs *regs)
 {
        irq_cascade_t *cascade;
        irq_desc_t *desc;
@@ -84,11 +84,32 @@ asmlinkage void irq_dispatch(unsigned int irq, struct pt_regs *regs)
                do_IRQ(irq, regs);
 }
 
-extern asmlinkage void vr41xx_handle_interrupt(void);
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+       unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
+
+       if (pending & CAUSEF_IP7)
+               do_IRQ(7, regs);
+       else if (pending & 0x7800) {
+               if (pending & CAUSEF_IP3)
+                       irq_dispatch(3, regs);
+               else if (pending & CAUSEF_IP4)
+                       irq_dispatch(4, regs);
+               else if (pending & CAUSEF_IP5)
+                       irq_dispatch(5, regs);
+               else if (pending & CAUSEF_IP6)
+                       irq_dispatch(6, regs);
+       } else if (pending & CAUSEF_IP2)
+               irq_dispatch(2, regs);
+       else if (pending & CAUSEF_IP0)
+               do_IRQ(0, regs);
+       else if (pending & CAUSEF_IP1)
+               do_IRQ(1, regs);
+       else
+               spurious_interrupt(regs);
+}
 
 void __init arch_init_irq(void)
 {
        mips_cpu_irq_init(MIPS_CPU_IRQ_BASE);
-
-       set_except_vector(0, vr41xx_handle_interrupt);
 }