MIPS: TXx9: Add board_be_init for TX4927/TX4938

[linux-2.6-omap-h63xx.git] / arch / mips / txx9 / generic / setup_tx4938.c

diff --git a/arch/mips/txx9/generic/setup_tx4938.c b/arch/mips/txx9/generic/setup_tx4938.c
index f3040b9ba0593df8596cb46c17264b336a2df42c..0d8517ad3ad0da6baf0725e9b476c3fd8bfe99e7 100644 (file)
--- a/arch/mips/txx9/generic/setup_tx4938.c
+++ b/arch/mips/txx9/generic/setup_tx4938.c
@@ -14,6 +14,10 @@
 #include <linux/ioport.h>
 #include <linux/delay.h>
 #include <linux/param.h>
+#include <linux/ptrace.h>
+#include <linux/mtd/physmap.h>
+#include <asm/reboot.h>
+#include <asm/traps.h>
 #include <asm/txx9irq.h>
 #include <asm/txx9tmr.h>
 #include <asm/txx9pio.h>
@@ -22,6 +26,10 @@
 
 static void __init tx4938_wdr_init(void)
 {
+       /* report watchdog reset status */
+       if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST)
+               pr_warning("Watchdog reset detected at 0x%lx\n",
+                          read_c0_errorepc());
        /* clear WatchDogReset (W1C) */
        tx4938_ccfg_set(TX4938_CCFG_WDRST);
        /* do reset on watchdog */
@@ -33,6 +41,47 @@ void __init tx4938_wdt_init(void)
        txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
 }
 
+static void tx4938_machine_restart(char *command)
+{
+       local_irq_disable();
+       pr_emerg("Rebooting (with %s watchdog reset)...\n",
+                (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) ?
+                "external" : "internal");
+       /* clear watchdog status */
+       tx4938_ccfg_set(TX4938_CCFG_WDRST);     /* W1C */
+       txx9_wdt_now(TX4938_TMR_REG(2) & 0xfffffffffULL);
+       while (!(____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDRST))
+               ;
+       mdelay(10);
+       if (____raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_WDREXEN) {
+               pr_emerg("Rebooting (with internal watchdog reset)...\n");
+               /* External WDRST failed.  Do internal watchdog reset */
+               tx4938_ccfg_clear(TX4938_CCFG_WDREXEN);
+       }
+       /* fallback */
+       (*_machine_halt)();
+}
+
+void show_registers(struct pt_regs *regs);
+static int tx4938_be_handler(struct pt_regs *regs, int is_fixup)
+{
+       int data = regs->cp0_cause & 4;
+       console_verbose();
+       pr_err("%cBE exception at %#lx\n", data ? 'D' : 'I', regs->cp0_epc);
+       pr_err("ccfg:%llx, toea:%llx\n",
+              (unsigned long long)____raw_readq(&tx4938_ccfgptr->ccfg),
+              (unsigned long long)____raw_readq(&tx4938_ccfgptr->toea));
+#ifdef CONFIG_PCI
+       tx4927_report_pcic_status();
+#endif
+       show_registers(regs);
+       panic("BusError!");
+}
+static void __init tx4938_be_init(void)
+{
+       board_be_handler = tx4938_be_handler;
+}
+
 static struct resource tx4938_sdram_resource[4];
 static struct resource tx4938_sram_resource;
 
@@ -47,6 +96,7 @@ void __init tx4938_setup(void)
 
        txx9_reg_res_init(TX4938_REV_PCODE(), TX4938_REG_BASE,
                          TX4938_REG_SIZE);
+       set_c0_config(TX49_CONF_CWFON);
 
        /* SDRAMC,EBUSC are configured by PROM */
        for (i = 0; i < 8; i++) {
@@ -227,6 +277,9 @@ void __init tx4938_setup(void)
                                   TX4938_CLKCTR_ETH1CKD);
                }
        }
+
+       _machine_restart = tx4938_machine_restart;
+       board_be_init = tx4938_be_init;
 }
 
 void __init tx4938_time_init(unsigned int tmrnr)
@@ -268,3 +321,16 @@ void __init tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1)
        if (addr1 && (pcfg & TX4938_PCFG_ETH1_SEL))
                txx9_ethaddr_init(TXX9_IRQ_BASE + TX4938_IR_ETH1, addr1);
 }
+
+void __init tx4938_mtd_init(int ch)
+{
+       struct physmap_flash_data pdata = {
+               .width = TX4938_EBUSC_WIDTH(ch) / 8,
+       };
+       unsigned long start = txx9_ce_res[ch].start;
+       unsigned long size = txx9_ce_res[ch].end - start + 1;
+
+       if (!(TX4938_EBUSC_CR(ch) & 0x8))
+               return; /* disabled */
+       txx9_physmap_flash_init(ch, start, size, &pdata);
+}