MIPS: TXx9: Cache fixup

[linux-2.6-omap-h63xx.git] / arch / mips / txx9 / generic / setup_tx3927.c

diff --git a/arch/mips/txx9/generic/setup_tx3927.c b/arch/mips/txx9/generic/setup_tx3927.c
index 0d09a0ff71e31a1922c8662f7d34092cc516c9a2..4bc2f859379d95fc8b136792dfb3731d0eda9d8b 100644 (file)
--- a/arch/mips/txx9/generic/setup_tx3927.c
+++ b/arch/mips/txx9/generic/setup_tx3927.c
@@ -13,8 +13,8 @@
 #include <linux/init.h>
 #include <linux/ioport.h>
 #include <linux/delay.h>
-#include <linux/serial_core.h>
 #include <linux/param.h>
+#include <linux/io.h>
 #include <asm/mipsregs.h>
 #include <asm/txx9irq.h>
 #include <asm/txx9tmr.h>
@@ -99,16 +99,14 @@ void __init tx3927_setup(void)
        txx9_gpio_init(TX3927_PIO_REG, 0, 16);
 
        conf = read_c0_conf();
-       if (!(conf & TX39_CONF_ICE))
-               printk(KERN_INFO "TX3927 I-Cache disabled.\n");
-       if (!(conf & TX39_CONF_DCE))
-               printk(KERN_INFO "TX3927 D-Cache disabled.\n");
-       else if (!(conf & TX39_CONF_WBON))
-               printk(KERN_INFO "TX3927 D-Cache WriteThrough.\n");
-       else if (!(conf & TX39_CONF_CWFON))
-               printk(KERN_INFO "TX3927 D-Cache WriteBack.\n");
-       else
-               printk(KERN_INFO "TX3927 D-Cache WriteBack (CWF) .\n");
+       if (conf & TX39_CONF_DCE) {
+               if (!(conf & TX39_CONF_WBON))
+                       pr_info("TX3927 D-Cache WriteThrough.\n");
+               else if (!(conf & TX39_CONF_CWFON))
+                       pr_info("TX3927 D-Cache WriteBack.\n");
+               else
+                       pr_info("TX3927 D-Cache WriteBack (CWF) .\n");
+       }
 }
 
 void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
@@ -119,23 +117,12 @@ void __init tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr)
        txx9_clocksource_init(TX3927_TMR_REG(src_tmrnr), TXX9_IMCLK);
 }
 
-void __init tx3927_setup_serial(unsigned int cts_mask)
+void __init tx3927_sio_init(unsigned int sclk, unsigned int cts_mask)
 {
-#ifdef CONFIG_SERIAL_TXX9
        int i;
-       struct uart_port req;
-
-       for (i = 0; i < 2; i++) {
-               memset(&req, 0, sizeof(req));
-               req.line = i;
-               req.iotype = UPIO_MEM;
-               req.membase = (unsigned char __iomem *)TX3927_SIO_REG(i);
-               req.mapbase = TX3927_SIO_REG(i);
-               req.irq = TXX9_IRQ_BASE + TX3927_IR_SIO(i);
-               if (!((1 << i) & cts_mask))
-                       req.flags |= UPF_BUGGY_UART /*HAVE_CTS_LINE*/;
-               req.uartclk = TXX9_IMCLK;
-               early_serial_txx9_setup(&req);
-       }
-#endif /* CONFIG_SERIAL_TXX9 */
+
+       for (i = 0; i < 2; i++)
+               txx9_sio_init(TX3927_SIO_REG(i),
+                             TXX9_IRQ_BASE + TX3927_IR_SIO(i),
+                             i, sclk, (1 << i) & cts_mask);
 }