#include <linux/pm.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
+#include <linux/gpio.h>
#include <asm/wbflush.h>
#include <asm/reboot.h>
-#include <asm/irq.h>
#include <asm/time.h>
-#include <asm/uaccess.h>
+#include <asm/txx9tmr.h>
#include <asm/io.h>
#include <asm/bootinfo.h>
#include <asm/tx4938/rbtx4938.h>
#ifdef CONFIG_SERIAL_TXX9
-#include <linux/tty.h>
-#include <linux/serial.h>
#include <linux/serial_core.h>
#endif
#include <linux/spi/spi.h>
#include <asm/tx4938/spi.h>
-#include <asm/gpio.h>
+#include <asm/txx9pio.h>
-extern void rbtx4938_time_init(void) __init;
extern char * __init prom_getcmdline(void);
static inline void tx4938_report_pcic_status1(struct tx4938_pcic_reg *pcicptr);
static int __init tx4938_pcibios_init(void)
{
unsigned long mem_base[2];
- unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0,TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
+ unsigned long mem_size[2] = {TX4938_PCIMEM_SIZE_0, TX4938_PCIMEM_SIZE_1}; /* MAX 128M,64K */
unsigned long io_base[2];
- unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0,TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
+ unsigned long io_size[2] = {TX4938_PCIIO_SIZE_0, TX4938_PCIIO_SIZE_1}; /* MAX 16M,64K */
/* TX4938 PCIC1: 64K MEM/IO is enough for ETH0,ETH1 */
int extarb = !(tx4938_ccfgptr->ccfg & TX4938_CCFG_PCIXARB);
printk(KERN_WARNING "seeprom: bad checksum.\n");
}
for (i = 0; i < 2; i++) {
- unsigned int slot = TX4938_PCIC_IDSEL_AD_TO_SLOT(31 - i);
- unsigned int id = (1 << 8) | PCI_DEVFN(slot, 0); /* bus 1 */
+ unsigned int id =
+ TXX9_IRQ_BASE + (i ? TX4938_IR_ETH1 : TX4938_IR_ETH0);
struct platform_device *pdev;
if (!(tx4938_ccfgptr->pcfg &
(i ? TX4938_PCFG_ETH1_SEL : TX4938_PCFG_ETH0_SEL)))
{
/* set SPI_SEL */
tx4938_ccfgptr->pcfg |= TX4938_PCFG_SPI_SEL;
- /* chip selects for SPI devices */
- tx4938_pioptr->dout |= (1 << SEEPROM1_CS);
- tx4938_pioptr->dir |= (1 << SEEPROM1_CS);
}
static struct resource rbtx4938_fpga_resource;
/* CCFG */
/* clear WatchDogReset,BusErrorOnWrite flag (W1C) */
tx4938_ccfgptr->ccfg |= TX4938_CCFG_WDRST | TX4938_CCFG_BEOW;
+ /* do reset on watchdog */
+ tx4938_ccfgptr->ccfg |= TX4938_CCFG_WR;
/* clear PCIC1 reset */
if (tx4938_ccfgptr->clkctr & TX4938_CLKCTR_PCIC1RST)
tx4938_ccfgptr->clkctr &= ~TX4938_CLKCTR_PCIC1RST;
}
/* TMR */
- /* disable all timers */
- for (i = 0; i < TX4938_NR_TMR; i++) {
- tx4938_tmrptr(i)->tcr = 0x00000020;
- tx4938_tmrptr(i)->tisr = 0;
- tx4938_tmrptr(i)->cpra = 0xffffffff;
- tx4938_tmrptr(i)->itmr = 0;
- tx4938_tmrptr(i)->ccdr = 0;
- tx4938_tmrptr(i)->pgmr = 0;
- }
+ for (i = 0; i < TX4938_NR_TMR; i++)
+ txx9_tmr_init(TX4938_TMR_REG(i) & 0xfffffffffULL);
/* enable DMA */
TX4938_WR64(0xff1fb150, TX4938_DMA_MCR_MSTEN);
TX4938_WR64(0xff1fb950, TX4938_DMA_MCR_MSTEN);
/* PIO */
- tx4938_pioptr->maskcpu = 0;
- tx4938_pioptr->maskext = 0;
+ __raw_writel(0, &tx4938_pioptr->maskcpu);
+ __raw_writel(0, &tx4938_pioptr->maskext);
/* TX4938 internal registers */
if (request_resource(&iomem_resource, &tx4938_reg_resource))
#endif /* CONFIG_PCI */
-/* We use onchip r4k counter or TMR timer as our system wide timer
- * interrupt running at 100HZ. */
-
-void __init rbtx4938_time_init(void)
+void __init plat_time_init(void)
{
mips_hpt_frequency = txx9_cpu_clock / 2;
+ if (tx4938_ccfgptr->ccfg & TX4938_CCFG_TINTDIS)
+ txx9_clockevent_init(TX4938_TMR_REG(0) & 0xfffffffffULL,
+ TXX9_IRQ_BASE + TX4938_IR_TMR(0),
+ txx9_gbus_clock / 2);
}
-void __init toshiba_rbtx4938_setup(void)
+void __init plat_mem_setup(void)
{
unsigned long long pcfg;
char *argptr;
/* GPIO support */
+int gpio_to_irq(unsigned gpio)
+{
+ return -EINVAL;
+}
+
+int irq_to_gpio(unsigned irq)
+{
+ return -EINVAL;
+}
+
static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
-static void rbtx4938_spi_gpio_set(unsigned gpio, int value)
+static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
+ int value)
{
u8 val;
unsigned long flags;
- gpio -= 16;
spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
val = *rbtx4938_spics_ptr;
if (value)
- val |= 1 << gpio;
+ val |= 1 << offset;
else
- val &= ~(1 << gpio);
+ val &= ~(1 << offset);
*rbtx4938_spics_ptr = val;
mmiowb();
spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
}
-static int rbtx4938_spi_gpio_dir_out(unsigned gpio, int value)
-{
- rbtx4938_spi_gpio_set(gpio, value);
- return 0;
-}
-
-static DEFINE_SPINLOCK(tx4938_gpio_lock);
-
-static int tx4938_gpio_get(unsigned gpio)
-{
- return tx4938_pioptr->din & (1 << gpio);
-}
-
-static void tx4938_gpio_set_raw(unsigned gpio, int value)
-{
- u32 val;
- val = tx4938_pioptr->dout;
- if (value)
- val |= 1 << gpio;
- else
- val &= ~(1 << gpio);
- tx4938_pioptr->dout = val;
-}
-
-static void tx4938_gpio_set(unsigned gpio, int value)
-{
- unsigned long flags;
- spin_lock_irqsave(&tx4938_gpio_lock, flags);
- tx4938_gpio_set_raw(gpio, value);
- mmiowb();
- spin_unlock_irqrestore(&tx4938_gpio_lock, flags);
-}
-
-static int tx4938_gpio_dir_in(unsigned gpio)
+static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
+ unsigned int offset, int value)
{
- spin_lock_irq(&tx4938_gpio_lock);
- tx4938_pioptr->dir &= ~(1 << gpio);
- mmiowb();
- spin_unlock_irq(&tx4938_gpio_lock);
+ rbtx4938_spi_gpio_set(chip, offset, value);
return 0;
}
-static int tx4938_gpio_dir_out(unsigned int gpio, int value)
-{
- spin_lock_irq(&tx4938_gpio_lock);
- tx4938_gpio_set_raw(gpio, value);
- tx4938_pioptr->dir |= 1 << gpio;
- mmiowb();
- spin_unlock_irq(&tx4938_gpio_lock);
- return 0;
-}
-
-int gpio_direction_input(unsigned gpio)
-{
- if (gpio < 16)
- return tx4938_gpio_dir_in(gpio);
- return -EINVAL;
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- if (gpio < 16)
- return tx4938_gpio_dir_out(gpio, value);
- if (gpio < 16 + 3)
- return rbtx4938_spi_gpio_dir_out(gpio, value);
- return -EINVAL;
-}
-
-int gpio_get_value(unsigned gpio)
-{
- if (gpio < 16)
- return tx4938_gpio_get(gpio);
- return 0;
-}
-
-void gpio_set_value(unsigned gpio, int value)
-{
- if (gpio < 16)
- tx4938_gpio_set(gpio, value);
- else
- rbtx4938_spi_gpio_set(gpio, value);
-}
+static struct gpio_chip rbtx4938_spi_gpio_chip = {
+ .set = rbtx4938_spi_gpio_set,
+ .direction_output = rbtx4938_spi_gpio_dir_out,
+ .label = "RBTX4938-SPICS",
+ .base = 16,
+ .ngpio = 3,
+};
/* SPI support */
spi_eeprom_register(SEEPROM1_CS);
spi_eeprom_register(16 + SEEPROM2_CS);
spi_eeprom_register(16 + SEEPROM3_CS);
+ gpio_request(16 + SRTC_CS, "rtc-rs5c348");
+ gpio_direction_output(16 + SRTC_CS, 0);
+ gpio_request(SEEPROM1_CS, "seeprom1");
+ gpio_direction_output(SEEPROM1_CS, 1);
+ gpio_request(16 + SEEPROM2_CS, "seeprom2");
+ gpio_direction_output(16 + SEEPROM2_CS, 1);
+ gpio_request(16 + SEEPROM3_CS, "seeprom3");
+ gpio_direction_output(16 + SEEPROM3_CS, 1);
txx9_spi_init(TX4938_SPI_REG & 0xfffffffffULL, RBTX4938_IRQ_IRC_SPI);
return 0;
}
-arch_initcall(rbtx4938_spi_init);
+
+static int __init rbtx4938_arch_init(void)
+{
+ txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, 16);
+ gpiochip_add(&rbtx4938_spi_gpio_chip);
+ return rbtx4938_spi_init();
+}
+arch_initcall(rbtx4938_arch_init);
+
+/* Watchdog support */
+
+static int __init txx9_wdt_init(unsigned long base)
+{
+ struct resource res = {
+ .start = base,
+ .end = base + 0x100 - 1,
+ .flags = IORESOURCE_MEM,
+ .parent = &tx4938_reg_resource,
+ };
+ struct platform_device *dev =
+ platform_device_register_simple("txx9wdt", -1, &res, 1);
+ return IS_ERR(dev) ? PTR_ERR(dev) : 0;
+}
+
+static int __init rbtx4938_wdt_init(void)
+{
+ return txx9_wdt_init(TX4938_TMR_REG(2) & 0xfffffffffULL);
+}
+device_initcall(rbtx4938_wdt_init);
/* Minimum CLK support */
{
if (!strcmp(id, "spi-baseclk"))
return (struct clk *)(txx9_gbus_clock / 2 / 4);
+ if (!strcmp(id, "imbus_clk"))
+ return (struct clk *)(txx9_gbus_clock / 2);
return ERR_PTR(-ENOENT);
}
EXPORT_SYMBOL(clk_get);
projects / linux-2.6-omap-h63xx.git / blobdiff