]> www.pilppa.org Git - linux-2.6-omap-h63xx.git/blobdiff - arch/mips/au1000/common/au1xxx_irqmap.c
[MIPS] Alchemy common code style cleanup
[linux-2.6-omap-h63xx.git] / arch / mips / au1000 / common / au1xxx_irqmap.c
index 37a10a01de9d30619c2a7c5feeabfac77cbb2c5f..c7ca1596394cc2a4e18c2f83c0f735ed7171d2b6 100644 (file)
 struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
 
 #if defined(CONFIG_SOC_AU1000)
-       { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -62,32 +62,32 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
 
 #elif defined(CONFIG_SOC_AU1500)
 
-       { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
-       { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
-       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -100,26 +100,26 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
 
 #elif defined(CONFIG_SOC_AU1100)
 
-       { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+       { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -128,33 +128,33 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
        { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       /*{ AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0},*/
-       { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       /* { AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0 }, */
+       { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
 
 #elif defined(CONFIG_SOC_AU1550)
 
-       { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
        { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
-       { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
        { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
        { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 },
-       { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -163,26 +163,26 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
+       { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
-       { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0 },
 
 #elif defined(CONFIG_SOC_AU1200)
 
-       { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 },
-       { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 },
-       { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0 },
        { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
@@ -191,10 +191,10 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
        { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
-       { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
+       { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0 },
        { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
-       { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
-       { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0},
+       { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0 },
+       { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0 },
 
 #else
 #error "Error: Unknown Alchemy SOC"
@@ -203,4 +203,3 @@ struct au1xxx_irqmap __initdata au1xxx_ic0_map[] = {
 };
 
 int __initdata au1xxx_ic0_nr_irqs = ARRAY_SIZE(au1xxx_ic0_map);
-