Blackfin arch: cleanup cache lock code

[linux-2.6-omap-h63xx.git] / arch / blackfin / mach-common / lock.S

diff --git a/arch/blackfin/mach-common/lock.S b/arch/blackfin/mach-common/lock.S
index 30b887e67dd6776def5ef53238ebe3fead7a6bbd..9daf01201e9fd86e111ffa4b85ca0e5dd4974788 100644 (file)
--- a/arch/blackfin/mach-common/lock.S
+++ b/arch/blackfin/mach-common/lock.S
@@ -28,13 +28,10 @@
  */
 
 #include <linux/linkage.h>
-#include <asm/cplb.h>
 #include <asm/blackfin.h>
 
 .text
 
-#ifdef CONFIG_BFIN_ICACHE_LOCK
-
 /* When you come here, it is assumed that
  * R0 - Which way to be locked
  */
@@ -189,18 +186,38 @@ ENTRY(_cache_lock)
        RTS;
 ENDPROC(_cache_lock)
 
-#endif /* BFIN_ICACHE_LOCK */
-
-/* Return the ILOC bits of IMEM_CONTROL
+/* Invalidate the Entire Instruction cache by
+ * disabling IMC bit
  */
+ENTRY(_invalidate_entire_icache)
+       [--SP] = ( R7:5);
 
-ENTRY(_read_iloc)
-       P1.H = HI(IMEM_CONTROL);
-       P1.L = LO(IMEM_CONTROL);
-       R1 = 0xF;
-       R0 = [P1];
-       R0 = R0 >> 3;
-       R0 = R0 & R1;
+       P0.L = LO(IMEM_CONTROL);
+       P0.H = HI(IMEM_CONTROL);
+       R7 = [P0];
+
+       /* Clear the IMC bit , All valid bits in the instruction
+        * cache are set to the invalid state
+        */
+       BITCLR(R7,IMC_P);
+       CLI R6;
+       SSYNC;          /* SSYNC required before invalidating cache. */
+       .align 8;
+       [P0] = R7;
+       SSYNC;
+       STI R6;
+
+       /* Configures the instruction cache agian */
+       R6 = (IMC | ENICPLB);
+       R7 = R7 | R6;
+
+       CLI R6;
+       SSYNC;          /* SSYNC required before writing to IMEM_CONTROL. */
+       .align 8;
+       [P0] = R7;
+       SSYNC;
+       STI R6;
 
+       ( R7:5) = [SP++];
        RTS;
-ENDPROC(_read_iloc)
+ENDPROC(_invalidate_entire_icache)