Blackfin arch: noMMU CPLB lookup tables can be in L1 SRAM

[linux-2.6-omap-h63xx.git] / arch / blackfin / kernel / cplb-nompu / cplbmgr.S

diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
index 985f3fc793f652b774357f9cba945dcc5a1db779..f4ca76c723941de69a614ddcb6e935d983f1f168 100644 (file)
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.S
@@ -629,15 +629,20 @@ ENTRY(_cplb_mgr)
        RTS;
 ENDPROC(_cplb_mgr)
 
+#ifdef CONFIG_CPLB_SWITCH_TAB_L1
+.section .l1.data
+#else
 .data
-.align 4;
-_page_size_table:
+#endif
+
+ENTRY(_page_size_table)
 .byte4 0x00000400;     /* 1K */
 .byte4 0x00001000;     /* 4K */
 .byte4 0x00100000;     /* 1M */
 .byte4 0x00400000;     /* 4M */
+END(_page_size_table)
 
-.align 4;
-_dcplb_preference:
+ENTRY(_dcplb_preference)
 .byte4 0x00000001;     /* valid bit */
 .byte4 0x00000002;     /* lock bit */
+END(_dcplb_preference)