OMAP2/3 clock: use clk->prcm_mod for all struct clk register addressing

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / include / mach / clock.h

diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 92f7c7238fcd9b94d019287dc1ea7ddd07fca472..f094d5b77779e34d91248bc917d3b05f7e3bd369 100644 (file)
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -15,6 +15,7 @@
 
 struct module;
 struct clk;
+struct clockdomain;
 
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 
@@ -30,7 +31,7 @@ struct clksel {
 };
 
 struct dpll_data {
-       void __iomem            *mult_div1_reg;
+       u16                     mult_div1_reg;
        u32                     mult_mask;
        u32                     div1_mask;
        u16                     last_rounded_m;
@@ -40,17 +41,19 @@ struct dpll_data {
        u16                     max_multiplier;
        u8                      max_divider;
        u32                     max_tolerance;
+       u16                     idlest_reg;
+       u32                     idlest_mask;
+       struct clk              *bypass_clk;
 #  if defined(CONFIG_ARCH_OMAP3)
+       u32                     freqsel_mask;
        u8                      modes;
-       void __iomem            *control_reg;
+       u16                     control_reg;
        u32                     enable_mask;
        u8                      auto_recal_bit;
        u8                      recal_en_bit;
        u8                      recal_st_bit;
-       void __iomem            *autoidle_reg;
+       u16                     autoidle_reg;
        u32                     autoidle_mask;
-       void __iomem            *idlest_reg;
-       u8                      idlest_bit;
 #  endif
 };
 
@@ -64,7 +67,7 @@ struct clk {
        struct clk              *parent;
        unsigned long           rate;
        __u32                   flags;
-       void __iomem            *enable_reg;
+       u16                     enable_reg;
        __u8                    enable_bit;
        __s8                    usecount;
        void                    (*recalc)(struct clk *);
@@ -75,10 +78,15 @@ struct clk {
        void                    (*disable)(struct clk *);
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
        u8                      fixed_div;
-       void __iomem            *clksel_reg;
+       u16                     clksel_reg;
        u32                     clksel_mask;
        const struct clksel     *clksel;
        struct dpll_data        *dpll_data;
+       union {
+               const char              *name;
+               struct clockdomain      *ptr;
+       } clkdm;
+       s16                     prcm_mod;
 #else
        __u8                    rate_offset;
        __u8                    src_offset;
@@ -107,16 +115,19 @@ struct clk_functions {
 
 extern unsigned int mpurate;
 
-extern int clk_init(struct clk_functions * custom_clocks);
+extern int clk_init(struct clk_functions *custom_clocks);
 extern int clk_register(struct clk *clk);
 extern void clk_unregister(struct clk *clk);
 extern void propagate_rate(struct clk *clk);
 extern void recalculate_root_clocks(void);
-extern void followparent_recalc(struct clk * clk);
+extern void followparent_recalc(struct clk *clk);
 extern void clk_allow_idle(struct clk *clk);
 extern void clk_deny_idle(struct clk *clk);
 extern int clk_get_usecount(struct clk *clk);
 extern void clk_enable_init_clocks(void);
+#ifdef CONFIG_CPU_FREQ
+extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+#endif
 
 /* Clock flags */
 #define RATE_CKCTL             (1 << 0)        /* Main fixed ratio clocks */
@@ -131,7 +142,7 @@ extern void clk_enable_init_clocks(void);
 #define DELAYED_APP            (1 << 9)        /* Delay application of clock */
 #define CONFIG_PARTICIPANT     (1 << 10)       /* Fundamental clock */
 #define ENABLE_ON_INIT         (1 << 11)       /* Enable upon framework init */
-#define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
+#define INVERT_ENABLE          (1 << 12)       /* 0 enables, 1 disables */
 /* bits 13-20 are currently free */
 #define CLOCK_IN_OMAP310       (1 << 21)
 #define CLOCK_IN_OMAP730       (1 << 22)
@@ -153,6 +164,13 @@ extern void clk_enable_init_clocks(void);
 
 #define RATE_IN_24XX           (RATE_IN_242X | RATE_IN_243X)
 
+/*
+ * clk.prcm_mod flags (possible since only the top byte in clk.prcm_mod
+ * is significant)
+ */
+#define PRCM_MOD_ADDR_MASK     0xff00
+#define CLK_REG_IN_PRM         (1 << 0)
+#define CLK_REG_IN_SCM         (1 << 1)
 
 /* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
 #define CORE_CLK_SRC_32K               0