unsigned long last_rounded_rate;
unsigned int rate_tolerance;
u16 max_multiplier;
+ u8 min_divider;
u8 max_divider;
u32 max_tolerance;
- u16 idlest_reg;
- u32 idlest_mask;
struct clk *bypass_clk;
+ u16 control_reg;
+ u32 enable_mask;
# if defined(CONFIG_ARCH_OMAP3)
+ u16 idlest_reg;
+ u32 idlest_mask;
u32 freqsel_mask;
u8 modes;
- u16 control_reg;
- u32 enable_mask;
u8 auto_recal_bit;
u8 recal_en_bit;
u8 recal_st_bit;
int id;
struct clk *parent;
unsigned long rate;
+ unsigned long temp_rate;
__u32 flags;
u32 enable_reg;
__u8 enable_bit;
__s8 usecount;
u8 idlest_bit;
- void (*recalc)(struct clk *);
+ void (*recalc)(struct clk *, unsigned long, u8);
int (*set_rate)(struct clk *, unsigned long);
long (*round_rate)(struct clk *, unsigned long);
void (*init)(struct clk *);
extern int clk_init(struct clk_functions *custom_clocks);
extern int clk_register(struct clk *clk);
extern void clk_unregister(struct clk *clk);
-extern void propagate_rate(struct clk *clk);
+extern void propagate_rate(struct clk *clk, u8 rate_storage);
extern void recalculate_root_clocks(void);
-extern void followparent_recalc(struct clk *clk);
+extern void followparent_recalc(struct clk *clk, unsigned long parent_rate,
+ u8 rate_storage);
extern void clk_allow_idle(struct clk *clk);
extern void clk_deny_idle(struct clk *clk);
extern int clk_get_usecount(struct clk *clk);
#define ENABLE_ON_INIT (1 << 11) /* Enable upon framework init */
#define INVERT_ENABLE (1 << 12) /* 0 enables, 1 disables */
#define WAIT_READY (1 << 13) /* wait for dev to leave idle */
-/* bits 14-20 are currently free */
+#define RECALC_ON_ENABLE (1 << 14) /* recalc/prop on ena/disa */
+/* bits 15-20 are currently free */
#define CLOCK_IN_OMAP310 (1 << 21)
#define CLOCK_IN_OMAP730 (1 << 22)
#define CLOCK_IN_OMAP1510 (1 << 23)
#define RATE_IN_24XX (RATE_IN_242X | RATE_IN_243X)
+/* rate_storage parameter flags */
+#define CURRENT_RATE 0
+#define TEMP_RATE 1
+
/*
* clk.prcm_mod flags (possible since only the top byte in clk.prcm_mod
* is significant)
#define CLK_REG_IN_PRM (1 << 0)
#define CLK_REG_IN_SCM (1 << 1)
-/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
-#define CORE_CLK_SRC_32K 0
-#define CORE_CLK_SRC_DPLL 1
-#define CORE_CLK_SRC_DPLL_X2 2
-
#endif