OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / include / mach / clock.h

diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index f26ad8c3e357f9cbee50dafaba7d8fecf1f45877..4eef580df527d60fce8a3331da9c5d5cd35abd3b 100644 (file)
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -39,6 +39,7 @@ struct dpll_data {
        unsigned long           last_rounded_rate;
        unsigned int            rate_tolerance;
        u16                     max_multiplier;
+       u8                      min_divider;
        u8                      max_divider;
        u32                     max_tolerance;
        u16                     idlest_reg;
@@ -67,7 +68,7 @@ struct clk {
        struct clk              *parent;
        unsigned long           rate;
        __u32                   flags;
-       u16                     enable_reg;
+       u32                     enable_reg;
        __u8                    enable_bit;
        __s8                    usecount;
        u8                      idlest_bit;
@@ -137,7 +138,7 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 #define VIRTUAL_CLOCK          (1 << 3)        /* Composite clock from table */
 #define ALWAYS_ENABLED         (1 << 4)        /* Clock cannot be disabled */
 #define ENABLE_REG_32BIT       (1 << 5)        /* Use 32-bit access */
-#define VIRTUAL_IO_ADDRESS     (1 << 6)        /* Clock in virtual address */
+
 #define CLOCK_IDLE_CONTROL     (1 << 7)
 #define CLOCK_NO_IDLE_PARENT   (1 << 8)
 #define DELAYED_APP            (1 << 9)        /* Delay application of clock */