OMAP3 clock: avoid invalid FREQSEL values during DPLL rate rounding

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / include / mach / clock.h

diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 24552b27cd45be38363175f48dadaa8b639fad31..4eef580df527d60fce8a3331da9c5d5cd35abd3b 100644 (file)
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -31,7 +31,7 @@ struct clksel {
 };
 
 struct dpll_data {
-       void __iomem            *mult_div1_reg;
+       u16                     mult_div1_reg;
        u32                     mult_mask;
        u32                     div1_mask;
        u16                     last_rounded_m;
@@ -39,20 +39,21 @@ struct dpll_data {
        unsigned long           last_rounded_rate;
        unsigned int            rate_tolerance;
        u16                     max_multiplier;
+       u8                      min_divider;
        u8                      max_divider;
        u32                     max_tolerance;
-       void __iomem            *idlest_reg;
+       u16                     idlest_reg;
        u32                     idlest_mask;
        struct clk              *bypass_clk;
 #  if defined(CONFIG_ARCH_OMAP3)
        u32                     freqsel_mask;
        u8                      modes;
-       void __iomem            *control_reg;
+       u16                     control_reg;
        u32                     enable_mask;
        u8                      auto_recal_bit;
        u8                      recal_en_bit;
        u8                      recal_st_bit;
-       void __iomem            *autoidle_reg;
+       u16                     autoidle_reg;
        u32                     autoidle_mask;
 #  endif
 };
@@ -67,7 +68,7 @@ struct clk {
        struct clk              *parent;
        unsigned long           rate;
        __u32                   flags;
-       void __iomem            *enable_reg;
+       u32                     enable_reg;
        __u8                    enable_bit;
        __s8                    usecount;
        u8                      idlest_bit;
@@ -79,7 +80,7 @@ struct clk {
        void                    (*disable)(struct clk *);
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
        u8                      fixed_div;
-       void __iomem            *clksel_reg;
+       u16                     clksel_reg;
        u32                     clksel_mask;
        const struct clksel     *clksel;
        struct dpll_data        *dpll_data;
@@ -137,7 +138,7 @@ extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
 #define VIRTUAL_CLOCK          (1 << 3)        /* Composite clock from table */
 #define ALWAYS_ENABLED         (1 << 4)        /* Clock cannot be disabled */
 #define ENABLE_REG_32BIT       (1 << 5)        /* Use 32-bit access */
-#define VIRTUAL_IO_ADDRESS     (1 << 6)        /* Clock in virtual address */
+
 #define CLOCK_IDLE_CONTROL     (1 << 7)
 #define CLOCK_NO_IDLE_PARENT   (1 << 8)
 #define DELAYED_APP            (1 << 9)        /* Delay application of clock */