REMOVE OMAP LEGACY CODE: Reset clocks and PM code to mainline

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / include / mach / clock.h

diff --git a/arch/arm/plat-omap/include/mach/clock.h b/arch/arm/plat-omap/include/mach/clock.h
index 719298554ed7ebc9647c931db05106e2b6c0e290..073a2c5569f02c16969d95ce72451fa072692055 100644 (file)
--- a/arch/arm/plat-omap/include/mach/clock.h
+++ b/arch/arm/plat-omap/include/mach/clock.h
@@ -17,11 +17,16 @@ struct module;
 struct clk;
 struct clockdomain;
 
+struct clkops {
+       int                     (*enable)(struct clk *);
+       void                    (*disable)(struct clk *);
+};
+
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 
 struct clksel_rate {
-       u8                      div;
        u32                     val;
+       u8                      div;
        u8                      flags;
 };
 
@@ -34,24 +39,28 @@ struct dpll_data {
        void __iomem            *mult_div1_reg;
        u32                     mult_mask;
        u32                     div1_mask;
+       struct clk              *clk_bypass;
+       struct clk              *clk_ref;
+       void __iomem            *control_reg;
+       u32                     enable_mask;
+       unsigned int            rate_tolerance;
+       unsigned long           last_rounded_rate;
        u16                     last_rounded_m;
        u8                      last_rounded_n;
-       unsigned long           last_rounded_rate;
-       unsigned int            rate_tolerance;
-       u16                     max_multiplier;
+       u8                      min_divider;
        u8                      max_divider;
        u32                     max_tolerance;
+       u16                     max_multiplier;
 #  if defined(CONFIG_ARCH_OMAP3)
        u8                      modes;
-       void __iomem            *control_reg;
-       u32                     enable_mask;
+       void __iomem            *autoidle_reg;
+       void __iomem            *idlest_reg;
+       u32                     autoidle_mask;
+       u32                     freqsel_mask;
+       u32                     idlest_mask;
        u8                      auto_recal_bit;
        u8                      recal_en_bit;
        u8                      recal_st_bit;
-       void __iomem            *autoidle_reg;
-       u32                     autoidle_mask;
-       void __iomem            *idlest_reg;
-       u8                      idlest_bit;
 #  endif
 };
 
@@ -59,21 +68,21 @@ struct dpll_data {
 
 struct clk {
        struct list_head        node;
-       struct module           *owner;
+       const struct clkops     *ops;
        const char              *name;
        int                     id;
        struct clk              *parent;
+       struct list_head        children;
+       struct list_head        sibling;        /* node for children */
        unsigned long           rate;
        __u32                   flags;
        void __iomem            *enable_reg;
-       __u8                    enable_bit;
-       __s8                    usecount;
-       void                    (*recalc)(struct clk *);
+       unsigned long           (*recalc)(struct clk *);
        int                     (*set_rate)(struct clk *, unsigned long);
        long                    (*round_rate)(struct clk *, unsigned long);
        void                    (*init)(struct clk *);
-       int                     (*enable)(struct clk *);
-       void                    (*disable)(struct clk *);
+       __u8                    enable_bit;
+       __s8                    usecount;
 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
        u8                      fixed_div;
        void __iomem            *clksel_reg;
@@ -99,7 +108,6 @@ struct clk_functions {
        long            (*clk_round_rate)(struct clk *clk, unsigned long rate);
        int             (*clk_set_rate)(struct clk *clk, unsigned long rate);
        int             (*clk_set_parent)(struct clk *clk, struct clk *parent);
-       struct clk *    (*clk_get_parent)(struct clk *clk);
        void            (*clk_allow_idle)(struct clk *clk);
        void            (*clk_deny_idle)(struct clk *clk);
        void            (*clk_disable_unused)(struct clk *clk);
@@ -110,42 +118,33 @@ struct clk_functions {
 
 extern unsigned int mpurate;
 
-extern int clk_init(struct clk_functions * custom_clocks);
+extern int clk_init(struct clk_functions *custom_clocks);
+extern void clk_init_one(struct clk *clk);
 extern int clk_register(struct clk *clk);
+extern void clk_reparent(struct clk *child, struct clk *parent);
 extern void clk_unregister(struct clk *clk);
 extern void propagate_rate(struct clk *clk);
 extern void recalculate_root_clocks(void);
-extern void followparent_recalc(struct clk * clk);
-extern void clk_allow_idle(struct clk *clk);
-extern void clk_deny_idle(struct clk *clk);
-extern int clk_get_usecount(struct clk *clk);
+extern unsigned long followparent_recalc(struct clk *clk);
 extern void clk_enable_init_clocks(void);
+#ifdef CONFIG_CPU_FREQ
+extern void clk_init_cpufreq_table(struct cpufreq_frequency_table **table);
+#endif
+
+extern const struct clkops clkops_null;
 
 /* Clock flags */
-#define RATE_CKCTL             (1 << 0)        /* Main fixed ratio clocks */
+/* bit 0 is free */
 #define RATE_FIXED             (1 << 1)        /* Fixed clock rate */
-#define RATE_PROPAGATES                (1 << 2)        /* Program children too */
-#define VIRTUAL_CLOCK          (1 << 3)        /* Composite clock from table */
-#define ALWAYS_ENABLED         (1 << 4)        /* Clock cannot be disabled */
+/* bits 2-4 are free */
 #define ENABLE_REG_32BIT       (1 << 5)        /* Use 32-bit access */
-#define VIRTUAL_IO_ADDRESS     (1 << 6)        /* Clock in virtual address */
 #define CLOCK_IDLE_CONTROL     (1 << 7)
 #define CLOCK_NO_IDLE_PARENT   (1 << 8)
 #define DELAYED_APP            (1 << 9)        /* Delay application of clock */
 #define CONFIG_PARTICIPANT     (1 << 10)       /* Fundamental clock */
 #define ENABLE_ON_INIT         (1 << 11)       /* Enable upon framework init */
 #define INVERT_ENABLE           (1 << 12)       /* 0 enables, 1 disables */
-/* bits 13-20 are currently free */
-#define CLOCK_IN_OMAP310       (1 << 21)
-#define CLOCK_IN_OMAP730       (1 << 22)
-#define CLOCK_IN_OMAP1510      (1 << 23)
-#define CLOCK_IN_OMAP16XX      (1 << 24)
-#define CLOCK_IN_OMAP242X      (1 << 25)
-#define CLOCK_IN_OMAP243X      (1 << 26)
-#define CLOCK_IN_OMAP343X      (1 << 27)       /* clocks common to all 343X */
-#define PARENT_CONTROLS_CLOCK  (1 << 28)
-#define CLOCK_IN_OMAP3430ES1   (1 << 29)       /* 3430ES1 clocks only */
-#define CLOCK_IN_OMAP3430ES2   (1 << 30)       /* 3430ES2 clocks only */
+/* bits 13-31 are currently free */
 
 /* Clksel_rate flags */
 #define DEFAULT_RATE           (1 << 0)
@@ -157,9 +156,4 @@ extern void clk_enable_init_clocks(void);
 #define RATE_IN_24XX           (RATE_IN_242X | RATE_IN_243X)
 
 
-/* CM_CLKSEL2_PLL.CORE_CLK_SRC options (24XX) */
-#define CORE_CLK_SRC_32K               0
-#define CORE_CLK_SRC_DPLL              1
-#define CORE_CLK_SRC_DPLL_X2           2
-
 #endif