Merge current mainline tree into linux-omap tree

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / gpio.c

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 56f4d1394d562bdfc652a2d7f13ee436042ed88c..4227d1e52f398fa1b5917325679fb9d7e4fd31c7 100644 (file)
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -149,6 +149,7 @@ struct gpio_bank {
        u32 saved_fallingdetect;
        u32 saved_risingdetect;
 #endif
+       u32 level_mask;
        spinlock_t lock;
 };
 
@@ -536,10 +537,9 @@ static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
                        bank->enabled_non_wakeup_gpios &= ~gpio_bit;
        }
 
-       /*
-        * FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only
-        * level triggering requested.
-        */
+       bank->level_mask = 
+               __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
+               __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 }
 #endif
 
@@ -649,6 +649,12 @@ static int gpio_irq_type(unsigned irq, unsigned type)
                irq_desc[irq].status |= type;
        }
        spin_unlock(&bank->lock);
+
+       if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
+               __set_irq_handler_unlocked(irq, handle_level_irq);
+       else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
+               __set_irq_handler_unlocked(irq, handle_edge_irq);
+                       
        return retval;
 }
 
@@ -1015,12 +1021,7 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                        isr &= 0x0000ffff;
 
                if (cpu_class_is_omap2()) {
-                       level_mask =
-                               __raw_readl(bank->base +
-                                       OMAP24XX_GPIO_LEVELDETECT0) |
-                               __raw_readl(bank->base +
-                                       OMAP24XX_GPIO_LEVELDETECT1);
-                       level_mask &= enabled;
+                       level_mask = bank->level_mask & enabled;
                }
 
                /* clear edge sensitive interrupts before handler(s) are
@@ -1045,51 +1046,13 @@ static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
                gpio_irq = bank->virtual_irq_start;
                for (; isr != 0; isr >>= 1, gpio_irq++) {
                        struct irq_desc *d;
-                       int irq_mask;
+
                        if (!(isr & 1))
                                continue;
                        d = irq_desc + gpio_irq;
-                       /* Don't run the handler if it's already running
-                        * or was disabled lazely.
-                        */
-                       if (unlikely((d->depth ||
-                                     (d->status & IRQ_INPROGRESS)))) {
-                               irq_mask = 1 <<
-                                       (gpio_irq - bank->virtual_irq_start);
-                               /* The unmasking will be done by
-                                * enable_irq in case it is disabled or
-                                * after returning from the handler if
-                                * it's already running.
-                                */
-                               _enable_gpio_irqbank(bank, irq_mask, 0);
-                               if (!d->depth) {
-                                       /* Level triggered interrupts
-                                        * won't ever be reentered
-                                        */
-                                       BUG_ON(level_mask & irq_mask);
-                                       d->status |= IRQ_PENDING;
-                               }
-                               continue;
-                       }
 
                        desc_handle_irq(gpio_irq, d);
-
-                       if (unlikely((d->status & IRQ_PENDING) && !d->depth)) {
-                               irq_mask = 1 <<
-                                       (gpio_irq - bank->virtual_irq_start);
-                               d->status &= ~IRQ_PENDING;
-                               _enable_gpio_irqbank(bank, irq_mask, 1);
-                               retrigger |= irq_mask;
-                       }
-               }
-
-               if (cpu_class_is_omap2()) {
-                       /* clear level sensitive interrupts after handler(s) */
-                       _enable_gpio_irqbank(bank, isr_saved & level_mask, 0);
-                       _clear_gpio_irqbank(bank, isr_saved & level_mask);
-                       _enable_gpio_irqbank(bank, isr_saved & level_mask, 1);
                }
-
        }
        /* if bank has any level sensitive GPIO pin interrupt
        configured, we must unmask the bank interrupt only after
@@ -1127,10 +1090,17 @@ static void gpio_mask_irq(unsigned int irq)
 static void gpio_unmask_irq(unsigned int irq)
 {
        unsigned int gpio = irq - IH_GPIO_BASE;
-       unsigned int gpio_idx = get_gpio_index(gpio);
        struct gpio_bank *bank = get_irq_chip_data(irq);
+       unsigned int irq_mask = 1 << get_gpio_index(gpio);
 
-       _set_gpio_irqenable(bank, gpio_idx, 1);
+       /* For level-triggered GPIOs, the clearing must be done after
+        * the HW source is cleared, thus after the handler has run */
+       if (bank->level_mask & irq_mask) {
+               _set_gpio_irqenable(bank, gpio, 0);
+               _clear_gpio_irqstatus(bank, gpio);
+       }
+               
+       _set_gpio_irqenable(bank, gpio, 1);
 }
 
 static struct irq_chip gpio_irq_chip = {