ARM: OMAP: Enable 24xx GPIO autoidling

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / gpio.c

diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index 8162eed8b500e697938fbc78e90bbb99392cfd24..037a4930ec6118a22d327ddf09c539e8e9c7fc22 100644 (file)
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -15,7 +15,6 @@
 #include <linux/module.h>
 #include <linux/sched.h>
 #include <linux/interrupt.h>
-#include <linux/ptrace.h>
 #include <linux/sysdev.h>
 #include <linux/err.h>
 #include <linux/clk.h>
@@ -410,7 +409,7 @@ static inline void set_24xx_gpio_triggering(void __iomem *base, int gpio, int tr
                trigger & __IRQT_RISEDGE);
        MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
                trigger & __IRQT_FALEDGE);
-       /* FIXME: Possibly do 'set_irq_handler(j, do_level_IRQ)' if only level
+       /* FIXME: Possibly do 'set_irq_handler(j, handle_level_irq)' if only level
         * triggering requested. */
 }
 
@@ -783,7 +782,7 @@ void omap_free_gpio(int gpio)
  * line's interrupt handler has been run, we may miss some nested
  * interrupts.
  */
-static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
+static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 {
        void __iomem *isr_reg = NULL;
        u32 isr;
@@ -853,7 +852,7 @@ static void gpio_irq_handler(unsigned int irq, struct irqdesc *desc)
 
                gpio_irq = bank->virtual_irq_start;
                for (; isr != 0; isr >>= 1, gpio_irq++) {
-                       struct irqdesc *d;
+                       struct irq_desc *d;
                        int irq_mask;
                        if (!(isr & 1))
                                continue;
@@ -974,10 +973,11 @@ static struct irq_chip gpio_irq_chip = {
 };
 
 static struct irq_chip mpuio_irq_chip = {
-       .name   = "MPUIO",
-       .ack    = mpuio_ack_irq,
-       .mask   = mpuio_mask_irq,
-       .unmask = mpuio_unmask_irq
+       .name     = "MPUIO",
+       .ack      = mpuio_ack_irq,
+       .mask     = mpuio_mask_irq,
+       .unmask   = mpuio_unmask_irq,
+       .set_type = gpio_irq_type,
 };
 
 static int initialized;
@@ -1082,6 +1082,10 @@ static int __init _omap_gpio_init(void)
                if (bank->method == METHOD_GPIO_24XX) {
                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
                        __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
+                       __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
+
+                       /* Initialize interface clock ungated, module enabled */
+                       __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
 
                        gpio_count = 32;
                }
@@ -1092,7 +1096,7 @@ static int __init _omap_gpio_init(void)
                                set_irq_chip(j, &mpuio_irq_chip);
                        else
                                set_irq_chip(j, &gpio_irq_chip);
-                       set_irq_handler(j, do_simple_IRQ);
+                       set_irq_handler(j, handle_simple_irq);
                        set_irq_flags(j, IRQF_VALID);
                }
                set_irq_chained_handler(bank->irq, gpio_irq_handler);
@@ -1104,6 +1108,12 @@ static int __init _omap_gpio_init(void)
        if (cpu_is_omap16xx())
                omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
 
+#ifdef CONFIG_ARCH_OMAP24XX
+       /* Enable autoidle for the OCP interface */
+       if (cpu_is_omap24xx())
+               omap_writel(1 << 0, 0x48019010);
+#endif
+
        return 0;
 }