ARM: OMAP: Fix omap mmu framework for omap1

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / dsp / omap2_dsp.h

diff --git a/arch/arm/plat-omap/dsp/omap2_dsp.h b/arch/arm/plat-omap/dsp/omap2_dsp.h
index af93be204a4b944c6672b6fae1fee1f3b5a08b1c..0dc43f0edcb78d0812c5ac79fb167c63e45552fa 100644 (file)
--- a/arch/arm/plat-omap/dsp/omap2_dsp.h
+++ b/arch/arm/plat-omap/dsp/omap2_dsp.h
@@ -77,75 +77,6 @@
 #define DSP_BOOT_ADR_API               0x010000
 #define DSP_BOOT_ADR_INTERNAL          0x024000
 
-/*
- * DSP MMU: mapped to 0xe2000000 -- use readX(), writeX()
- */
-#define DSP_MMU_BASE                   DSP_MMU_24XX_VIRT
-#define DSP_MMU_REVISION               (DSP_MMU_BASE + 0x00)
-#define DSP_MMU_SYSCONFIG              (DSP_MMU_BASE + 0x10)
-#define DSP_MMU_SYSSTATUS              (DSP_MMU_BASE + 0x14)
-#define DSP_MMU_IRQSTATUS              (DSP_MMU_BASE + 0x18)
-#define DSP_MMU_IRQENABLE              (DSP_MMU_BASE + 0x1c)
-#define DSP_MMU_WALKING_ST             (DSP_MMU_BASE + 0x40)
-#define DSP_MMU_CNTL                   (DSP_MMU_BASE + 0x44)
-#define DSP_MMU_FAULT_AD               (DSP_MMU_BASE + 0x48)
-#define DSP_MMU_TTB                    (DSP_MMU_BASE + 0x4c)
-#define DSP_MMU_LOCK                   (DSP_MMU_BASE + 0x50)
-#define DSP_MMU_LD_TLB                 (DSP_MMU_BASE + 0x54)
-#define DSP_MMU_CAM                    (DSP_MMU_BASE + 0x58)
-#define DSP_MMU_RAM                    (DSP_MMU_BASE + 0x5c)
-#define DSP_MMU_GFLUSH                 (DSP_MMU_BASE + 0x60)
-#define DSP_MMU_FLUSH_ENTRY            (DSP_MMU_BASE + 0x64)
-#define DSP_MMU_READ_CAM               (DSP_MMU_BASE + 0x68)
-#define DSP_MMU_READ_RAM               (DSP_MMU_BASE + 0x6c)
-#define DSP_MMU_EMU_FAULT_AD           (DSP_MMU_BASE + 0x70)
-
-#define DSP_MMU_SYSCONFIG_CLOCKACTIVITY_MASK   0x00000300
-#define DSP_MMU_SYSCONFIG_IDLEMODE_MASK                0x00000018
-#define DSP_MMU_SYSCONFIG_SOFTRESET            0x00000002
-#define DSP_MMU_SYSCONFIG_AUTOIDLE             0x00000001
-
-#define DSP_MMU_IRQ_MULTIHITFAULT      0x00000010
-#define DSP_MMU_IRQ_TABLEWALKFAULT     0x00000008
-#define DSP_MMU_IRQ_EMUMISS            0x00000004
-#define DSP_MMU_IRQ_TRANSLATIONFAULT   0x00000002
-#define DSP_MMU_IRQ_TLBMISS            0x00000001
-
-#define DSP_MMU_CNTL_EMUTLBUPDATE      0x00000008
-#define DSP_MMU_CNTL_TWLENABLE         0x00000004
-#define DSP_MMU_CNTL_MMUENABLE         0x00000002
-
-#define DSP_MMU_LOCK_BASE_MASK         0x00007c00
-#define DSP_MMU_LOCK_BASE_SHIFT                10
-#define DSP_MMU_LOCK_VICTIM_MASK       0x000001f0
-#define DSP_MMU_LOCK_VICTIM_SHIFT      4
-
-#define DSP_MMU_CAM_VATAG_MASK         0xfffff000
-#define DSP_MMU_CAM_P                  0x00000008
-#define DSP_MMU_CAM_V                  0x00000004
-#define DSP_MMU_CAM_PAGESIZE_MASK      0x00000003
-#define DSP_MMU_CAM_PAGESIZE_1MB       0x00000000
-#define DSP_MMU_CAM_PAGESIZE_64KB      0x00000001
-#define DSP_MMU_CAM_PAGESIZE_4KB       0x00000002
-#define DSP_MMU_CAM_PAGESIZE_16MB      0x00000003
-
-#define DSP_MMU_RAM_PADDR_MASK         0xfffff000
-#define DSP_MMU_RAM_ENDIANNESS         0x00000200
-#define DSP_MMU_RAM_ENDIANNESS_BIG     0x00000200
-#define DSP_MMU_RAM_ENDIANNESS_LITTLE  0x00000000
-#define DSP_MMU_RAM_ELEMENTSIZE_MASK   0x00000180
-#define DSP_MMU_RAM_ELEMENTSIZE_8      0x00000000
-#define DSP_MMU_RAM_ELEMENTSIZE_16     0x00000080
-#define DSP_MMU_RAM_ELEMENTSIZE_32     0x00000100
-#define DSP_MMU_RAM_ELEMENTSIZE_NONE   0x00000180
-#define DSP_MMU_RAM_MIXED              0x00000040
-
-#define DSP_MMU_GFLUSH_GFLUSH          0x00000001
-
-#define DSP_MMU_FLUSH_ENTRY_FLUSH_ENTRY        0x00000001
-
-#define DSP_MMU_LD_TLB_LD              0x00000001
-
 /*
  * DSP ICR
  */