ARM: OMAP: Fix omap mmu framework for omap1

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / dsp / omap1_dsp.h

diff --git a/arch/arm/plat-omap/dsp/omap1_dsp.h b/arch/arm/plat-omap/dsp/omap1_dsp.h
index 45fdb507d99b077fcd13f62e716d8fbfa2e72ae9..f4ec73eb19a886d0f94320dbd95d3b415c39cce8 100644 (file)
--- a/arch/arm/plat-omap/dsp/omap1_dsp.h
+++ b/arch/arm/plat-omap/dsp/omap1_dsp.h
@@ -100,80 +100,6 @@
 #define TC_ENDIANISM_SWAP_BYTE         0x00000000
 #define TC_ENDIANISM_EN                        0x00000001
 
-/*
- * DSP MMU
- */
-#define DSP_MMU_BASE                   (0xfefed200)
-#define DSP_MMU_PREFETCH               (DSP_MMU_BASE + 0x00)
-#define DSP_MMU_WALKING_ST             (DSP_MMU_BASE + 0x04)
-#define DSP_MMU_CNTL                   (DSP_MMU_BASE + 0x08)
-#define DSP_MMU_FAULT_AD_H             (DSP_MMU_BASE + 0x0c)
-#define DSP_MMU_FAULT_AD_L             (DSP_MMU_BASE + 0x10)
-#define DSP_MMU_FAULT_ST               (DSP_MMU_BASE + 0x14)
-#define DSP_MMU_IT_ACK                 (DSP_MMU_BASE + 0x18)
-#define DSP_MMU_TTB_H                  (DSP_MMU_BASE + 0x1c)
-#define DSP_MMU_TTB_L                  (DSP_MMU_BASE + 0x20)
-#define DSP_MMU_LOCK                   (DSP_MMU_BASE + 0x24)
-#define DSP_MMU_LD_TLB                 (DSP_MMU_BASE + 0x28)
-#define DSP_MMU_CAM_H                  (DSP_MMU_BASE + 0x2c)
-#define DSP_MMU_CAM_L                  (DSP_MMU_BASE + 0x30)
-#define DSP_MMU_RAM_H                  (DSP_MMU_BASE + 0x34)
-#define DSP_MMU_RAM_L                  (DSP_MMU_BASE + 0x38)
-#define DSP_MMU_GFLUSH                 (DSP_MMU_BASE + 0x3c)
-#define DSP_MMU_FLUSH_ENTRY            (DSP_MMU_BASE + 0x40)
-#define DSP_MMU_READ_CAM_H             (DSP_MMU_BASE + 0x44)
-#define DSP_MMU_READ_CAM_L             (DSP_MMU_BASE + 0x48)
-#define DSP_MMU_READ_RAM_H             (DSP_MMU_BASE + 0x4c)
-#define DSP_MMU_READ_RAM_L             (DSP_MMU_BASE + 0x50)
-
-#define DSP_MMU_CNTL_BURST_16MNGT_EN   0x0020
-#define DSP_MMU_CNTL_WTL_EN            0x0004
-#define DSP_MMU_CNTL_MMU_EN            0x0002
-#define DSP_MMU_CNTL_RESET_SW          0x0001
-
-#define DSP_MMU_FAULT_AD_H_DP          0x0100
-#define DSP_MMU_FAULT_AD_H_ADR_MASK    0x00ff
-
-#define DSP_MMU_FAULT_ST_PREF          0x0008
-#define DSP_MMU_FAULT_ST_PERM          0x0004
-#define DSP_MMU_FAULT_ST_TLB_MISS      0x0002
-#define DSP_MMU_FAULT_ST_TRANS         0x0001
-
-#define DSP_MMU_IT_ACK_IT_ACK          0x0001
-
-#define DSP_MMU_LOCK_BASE_MASK         0xfc00
-#define DSP_MMU_LOCK_BASE_SHIFT                10
-#define DSP_MMU_LOCK_VICTIM_MASK       0x03f0
-#define DSP_MMU_LOCK_VICTIM_SHIFT      4
-
-#define DSP_MMU_CAM_H_VA_TAG_H_MASK            0x0003
-
-#define DSP_MMU_CAM_L_VA_TAG_L1_MASK           0xc000
-#define DSP_MMU_CAM_L_VA_TAG_L2_MASK_1MB       0x0000
-#define DSP_MMU_CAM_L_VA_TAG_L2_MASK_64KB      0x3c00
-#define DSP_MMU_CAM_L_VA_TAG_L2_MASK_4KB       0x3fc0
-#define DSP_MMU_CAM_L_VA_TAG_L2_MASK_1KB       0x3ff0
-#define DSP_MMU_CAM_L_P                                0x0008
-#define DSP_MMU_CAM_L_V                                0x0004
-#define DSP_MMU_CAM_L_PAGESIZE_MASK            0x0003
-#define DSP_MMU_CAM_L_PAGESIZE_1MB             0x0000
-#define DSP_MMU_CAM_L_PAGESIZE_64KB            0x0001
-#define DSP_MMU_CAM_L_PAGESIZE_4KB             0x0002
-#define DSP_MMU_CAM_L_PAGESIZE_1KB             0x0003
-
-#define DSP_MMU_RAM_L_RAM_LSB_MASK     0xfc00
-#define DSP_MMU_RAM_L_AP_MASK          0x0300
-#define DSP_MMU_RAM_L_AP_NA            0x0000
-#define DSP_MMU_RAM_L_AP_RO            0x0200
-#define DSP_MMU_RAM_L_AP_FA            0x0300
-
-#define DSP_MMU_GFLUSH_GFLUSH          0x0001
-
-#define DSP_MMU_FLUSH_ENTRY_FLUSH_ENTRY        0x0001
-
-#define DSP_MMU_LD_TLB_RD              0x0002
-#define DSP_MMU_LD_TLB_LD              0x0001
-
 /*
  * DSP ICR
  */