Merge current mainline tree into linux-omap tree

[linux-2.6-omap-h63xx.git] / arch / arm / plat-omap / dma.c

diff --git a/arch/arm/plat-omap/dma.c b/arch/arm/plat-omap/dma.c
old mode 100644 (file)
new mode 100755 (executable)
index 692d2b4..5eaa468
--- a/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@ -278,14 +278,11 @@ void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
                u32 val;
 
                val = dma_read(CCR(lch));
-               val &= ~(3 << 19);
-               if (dma_trigger > 63)
-                       val |= 1 << 20;
-               if (dma_trigger > 31)
-                       val |= 1 << 19;
 
-               val &= ~(0x1f);
-               val |= (dma_trigger & 0x1f);
+               /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
+               val &= ~((3 << 19) | 0x1f);
+               val |= (dma_trigger & ~0x1f) << 14;
+               val |= dma_trigger & 0x1f;
 
                if (sync_mode & OMAP_DMA_SYNC_FRAME)
                        val |= 1 << 5;
@@ -712,6 +709,7 @@ int omap_request_dma(int dev_id, const char *dev_name,
        chan->dev_name = dev_name;
        chan->callback = callback;
        chan->data = data;
+       chan->flags = 0;
 
 #ifndef CONFIG_ARCH_OMAP1
        if (cpu_class_is_omap2()) {
@@ -1891,11 +1889,11 @@ static int omap2_dma_handle_ch(int ch)
                status = dma_read(CSR(ch));
        }
 
+       dma_write(status, CSR(ch));
+
        if (likely(dma_chan[ch].callback != NULL))
                dma_chan[ch].callback(ch, status, dma_chan[ch].data);
 
-       dma_write(status, CSR(ch));
-
        return 0;
 }
 
@@ -2419,6 +2417,19 @@ static int __init omap_init_dma(void)
        if (cpu_class_is_omap2())
                setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
 
+       /* Enable smartidle idlemodes and autoidle */
+       if (cpu_is_omap34xx()) {
+               u32 v = dma_read(OCP_SYSCONFIG);
+               v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
+                               DMA_SYSCONFIG_SIDLEMODE_MASK |
+                               DMA_SYSCONFIG_AUTOIDLE);
+               v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+                       DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+                       DMA_SYSCONFIG_AUTOIDLE);
+               dma_write(v , OCP_SYSCONFIG);
+       }
+
+
        /* FIXME: Update LCD DMA to work on 24xx */
        if (cpu_class_is_omap1()) {
                r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,