val = dma_read(CCR(lch));
val &= ~(3 << 19);
- if (dma_trigger > 63)
- val |= 1 << 20;
- if (dma_trigger > 31)
- val |= 1 << 19;
+ val |= ((dma_trigger & ~(0x1f)) << 14);
val &= ~(0x1f);
val |= (dma_trigger & 0x1f);
chan->dev_name = dev_name;
chan->callback = callback;
chan->data = data;
+ chan->flags = 0;
#ifndef CONFIG_ARCH_OMAP1
if (cpu_class_is_omap2()) {
if (cpu_class_is_omap2())
setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
+ /* Enable smartidle idlemodes and autoidle */
+ if (cpu_is_omap34xx()) {
+ u32 v = dma_read(OCP_SYSCONFIG);
+ v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
+ DMA_SYSCONFIG_SIDLEMODE_MASK |
+ DMA_SYSCONFIG_AUTOIDLE);
+ v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+ DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+ DMA_SYSCONFIG_AUTOIDLE);
+ dma_write(v , OCP_SYSCONFIG);
+ }
+
+
/* FIXME: Update LCD DMA to work on 24xx */
if (cpu_class_is_omap1()) {
r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,